Skip to content

Commit 61f879a

Browse files
micprogmicprog
committed
Update backend generation to send AWs when Ws are available
1 parent 8111705 commit 61f879a

16 files changed

+168
-42
lines changed

‎src/backend/idma_axi_write.sv

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,10 @@ module idma_axi_write #(
6868
/// AXI4+ATOP write manager port response
6969
input write_rsp_t write_rsp_i,
7070

71+
output logic w_chan_valid_o,
72+
output logic w_chan_ready_o,
73+
output logic w_chan_first_o,
74+
7175
/// Data from buffer
7276
input byte_t [StrbWidth-1:0] buffer_out_i,
7377
/// Valid from buffer
@@ -256,6 +260,10 @@ module idma_axi_write #(
256260
end
257261
end
258262

263+
// Channel management signals
264+
assign w_chan_valid_o = write_req_o.w_valid;
265+
assign w_chan_ready_o = write_rsp_i.w_ready;
266+
assign w_chan_first_o = first_w;
259267

260268
//--------------------------------------
261269
// Write response

‎src/backend/idma_axil_write.sv

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,10 @@ module idma_axil_write #(
6161
/// AXI Lite write manager port response
6262
input write_rsp_t write_rsp_i,
6363

64+
output logic w_chan_valid_o,
65+
output logic w_chan_ready_o,
66+
output logic w_chan_first_o,
67+
6468
/// Data from buffer
6569
input byte_t [StrbWidth-1:0] buffer_out_i,
6670
/// Valid from buffer
@@ -161,6 +165,11 @@ module idma_axil_write #(
161165
// we are ready for the next transfer internally, once the w last signal is applied
162166
assign w_dp_ready_o = write_happening;
163167

168+
// Channel management signals
169+
assign w_chan_valid_o = write_req_o.w_valid;
170+
assign w_chan_ready_o = write_rsp_i.w_ready;
171+
assign w_chan_first_o = 1'b1; // always first, no bursting
172+
164173
//--------------------------------------
165174
// Write response
166175
//--------------------------------------

‎src/backend/idma_axis_write.sv

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,10 @@ module idma_axis_write #(
6666
/// AXI Stream write manager port response
6767
input write_rsp_t write_rsp_i,
6868

69+
output logic w_chan_valid_o,
70+
output logic w_chan_ready_o,
71+
output logic w_chan_first_o,
72+
6973
/// Data from buffer
7074
input byte_t [StrbWidth-1:0] buffer_out_i,
7175
/// Valid from buffer
@@ -152,6 +156,10 @@ module idma_axis_write #(
152156
assign w_dp_req_ready_o = write_happening;
153157
assign aw_ready_o = write_happening;
154158

159+
assign w_chan_valid_o = write_req_o.tvalid;
160+
assign w_chan_ready_o = write_rsp_i.tready;
161+
assign w_chan_first_o = 1'b1; // always first, no AW channel
162+
155163
//--------------------------------------
156164
// Write response
157165
//--------------------------------------

‎src/backend/idma_channel_coupler.sv

Lines changed: 12 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -31,14 +31,12 @@ module idma_channel_coupler #(
3131
/// Testmode in
3232
input logic testmode_i,
3333

34-
/// R response valid
35-
input logic r_rsp_valid_i,
36-
/// R response ready
37-
input logic r_rsp_ready_i,
38-
/// First R response
39-
input logic r_rsp_first_i,
40-
/// Did the read originate from a decoupled request
41-
input logic r_decouple_aw_i,
34+
/// W request valid
35+
input logic w_req_valid_i,
36+
/// W request ready
37+
input logic w_req_ready_i,
38+
/// First W request
39+
input logic w_req_first_i,
4240
/// Is the `AW` in the queue a decoupled request?
4341
input logic aw_decouple_aw_i,
4442

@@ -87,8 +85,11 @@ module idma_channel_coupler #(
8785
// counter to keep track of AR to send
8886
cnt_t aw_to_send_d, aw_to_send_q;
8987

90-
// first signal -> an R has arrived that needs to free an AW
91-
assign first = r_rsp_valid_i & r_rsp_ready_i & r_rsp_first_i & !r_decouple_aw_i;
88+
logic aw_stall_d, aw_stall_q;
89+
90+
// first signal -> a W has data that needs to free an AW
91+
assign first = w_req_valid_i & w_req_first_i & ~aw_stall_q;
92+
assign aw_stall_d = w_req_valid_i & ~w_req_ready_i;
9293

9394
// stream fifo to hold AWs back
9495
stream_fifo_optimal_wrap #(
@@ -180,6 +181,7 @@ module idma_channel_coupler #(
180181

181182
// state
182183
`FF(aw_to_send_q, aw_to_send_d, '0, clk_i, rst_ni)
184+
`FF(aw_stall_q, aw_stall_d, '0, clk_i, rst_ni)
183185

184186

185187
endmodule

‎src/backend/idma_init_write.sv

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,10 @@ module idma_init_write #(
6262
/// INIT write manager port response
6363
input write_rsp_t write_rsp_i,
6464

65+
output logic w_chan_valid_o,
66+
output logic w_chan_ready_o,
67+
output logic w_chan_first_o,
68+
6569
/// Data from buffer
6670
input byte_t [StrbWidth-1:0] buffer_out_i,
6771
/// Valid from buffer
@@ -151,6 +155,11 @@ module idma_init_write #(
151155
assign w_dp_ready_o = write_happening;
152156
assign write_meta_ready_o = write_happening;
153157

158+
// Channel management signals
159+
assign w_chan_valid_o = write_req_o.req_valid;
160+
assign w_chan_ready_o = write_rsp_i.req_ready;
161+
assign w_chan_first_o = 1'b1; // always first, no AW channel
162+
154163
//--------------------------------------
155164
// Write response
156165
//--------------------------------------

‎src/backend/idma_obi_write.sv

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,10 @@ module idma_obi_write #(
6161
/// OBI write manager port response
6262
input write_rsp_t write_rsp_i,
6363

64+
output logic w_chan_valid_o,
65+
output logic w_chan_ready_o,
66+
output logic w_chan_first_o,
67+
6468
/// Data from buffer
6569
input byte_t [StrbWidth-1:0] buffer_out_i,
6670
/// Valid from buffer
@@ -153,6 +157,11 @@ module idma_obi_write #(
153157
assign w_dp_ready_o = write_happening;
154158
assign aw_ready_o = write_happening;
155159

160+
// Channel management signals
161+
assign w_chan_valid_o = write_req_o.req;
162+
assign w_chan_ready_o = write_rsp_i.gnt;
163+
assign w_chan_first_o = 1'b1; // always first, no bursting
164+
156165
//--------------------------------------
157166
// Write response
158167
//--------------------------------------

‎src/backend/idma_tilelink_write.sv

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,6 +70,10 @@ module idma_tilelink_write #(
7070
/// TileLink write manager port response
7171
input write_rsp_t write_rsp_i,
7272

73+
output logic w_chan_valid_o,
74+
output logic w_chan_ready_o,
75+
output logic w_chan_first_o,
76+
7377
/// Data from buffer
7478
input byte_t [StrbWidth-1:0] buffer_out_i,
7579
/// Valid from buffer
@@ -254,6 +258,10 @@ module idma_tilelink_write #(
254258
end
255259
end
256260

261+
// Channel management signals
262+
assign w_chan_valid_o = write_req_o.a_valid;
263+
assign w_chan_ready_o = write_rsp_i.a_ready;
264+
assign w_chan_first_o = first_w;
257265

258266
//--------------------------------------
259267
// Write response

‎src/backend/tpl/idma_backend.sv.tpl

Lines changed: 19 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -371,9 +371,13 @@ _rsp_t ${protocol}_write_rsp_i,
371371
logic rsp_valid;
372372
logic rsp_ready;
373373

374-
// Respone Channel valid and ready -> needed for bursting
375-
logic r_chan_valid;
376-
logic r_chan_ready;
374+
// // Respone Channel valid and ready -> needed for bursting
375+
// logic r_chan_valid;
376+
// logic r_chan_ready;
377+
378+
logic w_chan_valid;
379+
logic w_chan_ready;
380+
logic w_chan_first;
377381

378382
//--------------------------------------
379383
// Reject Zero Length Transfers
@@ -770,8 +774,11 @@ _rsp_t ${protocol}_write_rsp_i,
770774
.r_dp_busy_o ( busy_o.r_dp_busy ),
771775
.w_dp_busy_o ( busy_o.w_dp_busy ),
772776
.buffer_busy_o ( busy_o.buffer_busy ),
773-
.r_chan_ready_o ( r_chan_ready ),
774-
.r_chan_valid_o ( r_chan_valid )
777+
.w_chan_valid_o ( w_chan_valid ),
778+
.w_chan_ready_o ( w_chan_ready ),
779+
.w_chan_first_o ( w_chan_first )
780+
// .r_chan_ready_o ( r_chan_ready ),
781+
// .r_chan_valid_o ( r_chan_valid )
775782
);
776783

777784
//--------------------------------------
@@ -803,10 +810,13 @@ _rsp_t ${protocol}_write_rsp_i,
803810
.clk_i ( clk_i ),
804811
.rst_ni ( rst_ni ),
805812
.testmode_i ( testmode_i ),
806-
.r_rsp_valid_i ( r_chan_valid ),
807-
.r_rsp_ready_i ( r_chan_ready ),
808-
.r_rsp_first_i ( r_dp_rsp.first ),
809-
.r_decouple_aw_i ( r_dp_req_out.decouple_aw ),
813+
.w_req_valid_i ( w_chan_valid ),
814+
.w_req_ready_i ( w_chan_ready ),
815+
.w_req_first_i ( w_chan_first ),
816+
// .r_rsp_valid_i ( r_chan_valid ),
817+
// .r_rsp_ready_i ( r_chan_ready ),
818+
// .r_rsp_first_i ( r_dp_rsp.first ),
819+
// .r_decouple_aw_i ( r_dp_req_out.decouple_aw ),
810820
.aw_decouple_aw_i ( \
811821
% if one_write_port:
812822
w_req.decouple_aw\

‎src/backend/tpl/idma_transport_layer.sv.tpl

Lines changed: 47 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -172,9 +172,12 @@ _rsp_t ${protocol}_write_rsp_i,
172172
/// Datapath poison signal
173173
input logic dp_poison_i,
174174

175-
/// Response channel valid and ready
176-
output logic r_chan_ready_o,
177-
output logic r_chan_valid_o,
175+
// /// Response channel valid and ready
176+
// output logic r_chan_ready_o,
177+
// output logic r_chan_valid_o,
178+
output logic w_chan_valid_o,
179+
output logic w_chan_ready_o,
180+
output logic w_chan_first_o,
178181

179182
/// Read part of the datapath is busy
180183
output logic r_dp_busy_o,
@@ -231,7 +234,7 @@ _rsp_t ${protocol}_write_rsp_i,
231234
% if not one_read_port:
232235

233236
// Read multiplexed signals
234-
logic\
237+
// logic\
235238
% for index, protocol in enumerate(used_read_protocols):
236239
${protocol}_r_chan_valid\
237240
% if index == len(used_read_protocols)-1:
@@ -240,7 +243,7 @@ _rsp_t ${protocol}_write_rsp_i,
240243
,\
241244
% endif
242245
%endfor
243-
logic\
246+
// logic\
244247
% for index, protocol in enumerate(used_read_protocols):
245248
${protocol}_r_chan_ready\
246249
% if index == len(used_read_protocols)-1:
@@ -292,6 +295,33 @@ _rsp_t ${protocol}_write_rsp_i,
292295
// Write multiplexed signals
293296
logic\
294297
% for index, protocol in enumerate(used_write_protocols):
298+
${protocol}_w_chan_valid\
299+
% if index == len(used_write_protocols)-1:
300+
;
301+
% else:
302+
,\
303+
% endif
304+
%endfor
305+
logic\
306+
% for index, protocol in enumerate(used_write_protocols):
307+
${protocol}_w_chan_ready\
308+
% if index == len(used_write_protocols)-1:
309+
;
310+
% else:
311+
,\
312+
% endif
313+
%endfor
314+
logic\
315+
% for index, protocol in enumerate(used_write_protocols):
316+
${protocol}_w_chan_first\
317+
% if index == len(used_write_protocols)-1:
318+
;
319+
% else:
320+
,\
321+
% endif
322+
%endfor
323+
logic\
324+
% for index, protocol in enumerate(used_write_protocols):
295325
${protocol}_w_dp_rsp_valid\
296326
% if index == len(used_write_protocols)-1:
297327
;
@@ -376,8 +406,8 @@ ${rendered_read_ports[read_port]}
376406
case(r_dp_req_i.src_protocol)
377407
% for rp in used_read_protocols:
378408
idma_pkg::${database[rp]['protocol_enum']}: begin
379-
r_chan_valid_o = ${rp}_r_chan_valid;
380-
r_chan_ready_o = ${rp}_r_chan_ready;
409+
//r_chan_valid_o = ${rp}_r_chan_valid;
410+
//r_chan_ready_o = ${rp}_r_chan_ready;
381411

382412
r_dp_ready_o = ${rp}_r_dp_ready;
383413
r_dp_rsp_o = ${rp}_r_dp_rsp;
@@ -388,8 +418,8 @@ ${rendered_read_ports[read_port]}
388418
end
389419
% endfor
390420
default: begin
391-
r_chan_valid_o = 1'b0;
392-
r_chan_ready_o = 1'b0;
421+
//r_chan_valid_o = 1'b0;
422+
//r_chan_ready_o = 1'b0;
393423

394424
r_dp_ready_o = 1'b0;
395425
r_dp_rsp_o = '0;
@@ -400,8 +430,8 @@ ${rendered_read_ports[read_port]}
400430
end
401431
endcase
402432
end else begin
403-
r_chan_valid_o = 1'b0;
404-
r_chan_ready_o = 1'b0;
433+
//r_chan_valid_o = 1'b0;
434+
//r_chan_ready_o = 1'b0;
405435

406436
r_dp_ready_o = 1'b0;
407437
r_dp_rsp_o = '0;
@@ -475,11 +505,17 @@ ${rendered_read_ports[read_port]}
475505
idma_pkg::${database[wp]['protocol_enum']}: begin
476506
w_dp_req_ready = ${wp}_w_dp_ready;
477507
buffer_out_ready = ${wp}_buffer_out_ready;
508+
w_chan_valid_o = ${wp}_w_chan_valid;
509+
w_chan_ready_o = ${wp}_w_chan_ready;
510+
w_chan_first_o = ${wp}_w_chan_first;
478511
end
479512
% endfor
480513
default: begin
481514
w_dp_req_ready = 1'b0;
482515
buffer_out_ready = '0;
516+
w_chan_valid_o = 1'b0;
517+
w_chan_ready_o = 1'b0;
518+
w_chan_first_o = 1'b0;
483519
end
484520
endcase
485521
end

‎src/db/idma_axi.yml

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -92,8 +92,8 @@ read_template: |
9292
.ar_ready_o ( ${read_meta_ready} ),
9393
.read_req_o ( ${read_request} ),
9494
.read_rsp_i ( ${read_response} ),
95-
.r_chan_valid_o ( ${r_chan_valid} ),
96-
.r_chan_ready_o ( ${r_chan_ready} ),
95+
.r_chan_valid_o ( /*${r_chan_valid}*/ ),
96+
.r_chan_ready_o ( /*${r_chan_ready}*/ ),
9797
.buffer_in_o ( ${buffer_in} ),
9898
.buffer_in_valid_o ( ${buffer_in_valid} ),
9999
.buffer_in_ready_i ( buffer_in_ready )
@@ -125,6 +125,9 @@ write_template: |
125125
.aw_ready_o ( ${write_meta_ready} ),
126126
.write_req_o ( ${write_request} ),
127127
.write_rsp_i ( ${write_response} ),
128+
.w_chan_valid_o ( ${w_chan_valid} ),
129+
.w_chan_ready_o ( ${w_chan_ready} ),
130+
.w_chan_first_o ( ${w_chan_first} ),
128131
.buffer_out_i ( buffer_out_shifted ),
129132
.buffer_out_valid_i ( buffer_out_valid_shifted ),
130133
.buffer_out_ready_o ( ${buffer_out_ready} )

0 commit comments

Comments
 (0)