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msc24h31 Lucia Luzi (luzil)
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frontend: added signals for init and obi
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‎src/frontend/inst64/idma_inst64_top.sv

Lines changed: 59 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,10 @@ module idma_inst64_top #(
2424
parameter type axi_aw_chan_t = logic,
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parameter type axi_req_t = logic,
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parameter type axi_res_t = logic,
27+
parameter type init_req_t = logic,
28+
parameter type init_rsp_t = logic,
29+
parameter type obi_req_t = logic,
30+
parameter type obi_res_t = logic,
2731
parameter type acc_req_t = logic,
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parameter type acc_res_t = logic,
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parameter type dma_events_t = logic
@@ -34,6 +38,12 @@ module idma_inst64_top #(
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// AXI4 bus
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output axi_req_t [NumChannels-1:0] axi_req_o,
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input axi_res_t [NumChannels-1:0] axi_res_i,
41+
// Memory Init
42+
output init_req_t [NumChannels-1:0] init_req_o,
43+
input init_res_t [NumChannels-1:0] init_res_i,
44+
// OBI interconnect
45+
output obi_req_t [NumChannels-1:0] obi_req_o,
46+
input obi_res_t [NumChannels-1:0] obi_res_i,
3747
// debug output
3848
output logic [NumChannels-1:0] busy_o,
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// accelerator interface
@@ -102,6 +112,14 @@ module idma_inst64_top #(
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axi_req_t [NumChannels-1:0] axi_read_req, axi_write_req;
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axi_res_t [NumChannels-1:0] axi_read_rsp, axi_write_rsp;
104114

115+
// internal Init channels
116+
init_req_t [NumChannels-1:0] init_read_req, init_write_req;
117+
init_res_t [NumChannels-1:0] init_read_rsp, init_write_rsp;
118+
119+
// internal OBI channels
120+
obi_req_t [NumChannels-1:0] obi_read_req, obi_write_req;
121+
obi_res_t [NumChannels-1:0] obi_read_rsp, obi_write_rsp;
122+
105123
// backend signals
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idma_req_t [NumChannels-1:0] idma_req;
107125
logic [NumChannels-1:0] idma_req_valid;
@@ -149,7 +167,7 @@ module idma_inst64_top #(
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// Backend instantiation
150168
//--------------------------------------
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for (genvar c = 0; c < NumChannels; c++) begin : gen_backend
152-
idma_backend_rw_axi #(
170+
idma_backend_rw_axi_rw_init_rw_obi #(
153171
.DataWidth ( AxiDataWidth ),
154172
.AddrWidth ( AxiAddrWidth ),
155173
.UserWidth ( AxiUserWidth ),
@@ -171,41 +189,53 @@ module idma_inst64_top #(
171189
.idma_busy_t ( idma_pkg::idma_busy_t ),
172190
.axi_req_t ( axi_req_t ),
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.axi_rsp_t ( axi_res_t ),
192+
.init_req_t ( init_req_t ),
193+
.init_rsp_t ( init_res_t ),
194+
.obi_req_t ( obi_req_t ),
195+
.obi_rsp_t ( obi_res_t ),
174196
.read_meta_channel_t ( read_meta_channel_t ),
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.write_meta_channel_t ( write_meta_channel_t )
176-
) i_idma_backend_rw_axi (
198+
) i_idma_backend_rw_axi_rw_init_rw_obi (
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.clk_i,
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.rst_ni,
179201
.testmode_i,
180-
.idma_req_i ( idma_req [c] ),
181-
.req_valid_i ( idma_req_valid [c] ),
182-
.req_ready_o ( idma_req_ready [c] ),
183-
.idma_rsp_o ( idma_rsp [c] ),
184-
.rsp_valid_o ( idma_rsp_valid [c] ),
185-
.rsp_ready_i ( idma_rsp_ready [c] ),
186-
.idma_eh_req_i ( '0 ),
187-
.eh_req_valid_i ( 1'b0 ),
188-
.eh_req_ready_o ( /* NC */ ),
189-
.axi_read_req_o ( axi_read_req [c] ),
190-
.axi_read_rsp_i ( axi_read_rsp [c] ),
191-
.axi_write_req_o ( axi_write_req [c] ),
192-
.axi_write_rsp_i ( axi_write_rsp [c] ),
193-
.busy_o ( idma_busy [c] )
202+
.idma_req_i ( idma_req [c] ),
203+
.req_valid_i ( idma_req_valid [c] ),
204+
.req_ready_o ( idma_req_ready [c] ),
205+
.idma_rsp_o ( idma_rsp [c] ),
206+
.rsp_valid_o ( idma_rsp_valid [c] ),
207+
.rsp_ready_i ( idma_rsp_ready [c] ),
208+
.idma_eh_req_i ( '0 ),
209+
.eh_req_valid_i ( 1'b0 ),
210+
.eh_req_ready_o ( /* NC */ ),
211+
.axi_read_req_o ( axi_read_req [c] ),
212+
.axi_read_rsp_i ( axi_read_rsp [c] ),
213+
.init_read_req_o ( init_read_req [c] ),
214+
.init_read_rsp_i ( init_read_rsp [c] ),
215+
.obi_read_req_o ( obi_read_req [c] ),
216+
.obi_read_rsp_i ( obi_read_rsp [c] ),
217+
.axi_write_req_o ( axi_write_req [c] ),
218+
.axi_write_rsp_i ( axi_write_rsp [c] ),
219+
.init_write_req_o ( init_write_req [c] ),
220+
.init_write_rsp_i ( init_write_rsp [c] ),
221+
.obi_write_req_o ( obi_write_req [c] ),
222+
.obi_write_rsp_i ( obi_write_rsp [c] ),
223+
.busy_o ( idma_busy [c] )
194224
);
195225

196-
axi_rw_join #(
197-
.axi_req_t ( axi_req_t ),
198-
.axi_resp_t ( axi_res_t )
199-
) i_axi_rw_join (
200-
.clk_i,
201-
.rst_ni,
202-
.slv_read_req_i ( axi_read_req [c] ),
203-
.slv_read_resp_o ( axi_read_rsp [c] ),
204-
.slv_write_req_i ( axi_write_req [c] ),
205-
.slv_write_resp_o ( axi_write_rsp [c] ),
206-
.mst_req_o ( axi_req_o [c] ),
207-
.mst_resp_i ( axi_res_i [c] )
208-
);
226+
// axi_rw_join #(
227+
// .axi_req_t ( axi_req_t ),
228+
// .axi_resp_t ( axi_res_t )
229+
// ) i_axi_rw_join (
230+
// .clk_i,
231+
// .rst_ni,
232+
// .slv_read_req_i ( axi_read_req [c] ),
233+
// .slv_read_resp_o ( axi_read_rsp [c] ),
234+
// .slv_write_req_i ( axi_write_req [c] ),
235+
// .slv_write_resp_o ( axi_write_rsp [c] ),
236+
// .mst_req_o ( axi_req_o [c] ),
237+
// .mst_resp_i ( axi_res_i [c] )
238+
// );
209239

210240
assign busy_o[c] = (|idma_busy[c]) | idma_nd_busy[c];
211241
end

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