From dcedc661349dbe3c5fc9d1cff3b73083f6f632cd Mon Sep 17 00:00:00 2001 From: "msc24h31 Lucia Luzi (luzil)" Date: Thu, 28 Nov 2024 16:10:30 +0100 Subject: [PATCH 01/18] add .venv --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 350d24bf..f0b54d46 100644 --- a/.gitignore +++ b/.gitignore @@ -11,3 +11,4 @@ working_dir bender morty todo +.venv \ No newline at end of file From f2757b888d8b958b9c88fddae2ea7424b6890868 Mon Sep 17 00:00:00 2001 From: "msc24h31 Lucia Luzi (luzil)" Date: Thu, 28 Nov 2024 16:11:21 +0100 Subject: [PATCH 02/18] add rw idma variant --- idma.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/idma.mk b/idma.mk index c239168e..11edd9e6 100644 --- a/idma.mk +++ b/idma.mk @@ -29,7 +29,7 @@ IDMA_BASE_IDS := \ IDMA_OCCAMY_IDS := \ r_obi_rw_init_w_axi \ r_axi_rw_init_rw_obi -IDMA_ADD_IDS ?= +IDMA_ADD_IDS ?= rw_axi_rw_init_rw_obi IDMA_BACKEND_IDS := $(IDMA_BASE_IDS) $(IDMA_OCCAMY_IDS) $(IDMA_ADD_IDS) # generated frontends From 094b58c85bb3eb3d50b47b66ef07623d781d7ad5 Mon Sep 17 00:00:00 2001 From: "msc24h31 Lucia Luzi (luzil)" Date: Mon, 9 Dec 2024 15:28:51 +0100 Subject: [PATCH 03/18] frontend: added signals for init and obi --- src/frontend/inst64/idma_inst64_top.sv | 88 +++++++++++++++++--------- 1 file changed, 59 insertions(+), 29 deletions(-) diff --git a/src/frontend/inst64/idma_inst64_top.sv b/src/frontend/inst64/idma_inst64_top.sv index cd702d06..f27cb79c 100644 --- a/src/frontend/inst64/idma_inst64_top.sv +++ b/src/frontend/inst64/idma_inst64_top.sv @@ -24,6 +24,10 @@ module idma_inst64_top #( parameter type axi_aw_chan_t = logic, parameter type axi_req_t = logic, parameter type axi_res_t = logic, + parameter type init_req_t = logic, + parameter type init_rsp_t = logic, + parameter type obi_req_t = logic, + parameter type obi_res_t = logic, parameter type acc_req_t = logic, parameter type acc_res_t = logic, parameter type dma_events_t = logic @@ -34,6 +38,12 @@ module idma_inst64_top #( // AXI4 bus output axi_req_t [NumChannels-1:0] axi_req_o, input axi_res_t [NumChannels-1:0] axi_res_i, + // Memory Init + output init_req_t [NumChannels-1:0] init_req_o, + input init_res_t [NumChannels-1:0] init_res_i, + // OBI interconnect + output obi_req_t [NumChannels-1:0] obi_req_o, + input obi_res_t [NumChannels-1:0] obi_res_i, // debug output output logic [NumChannels-1:0] busy_o, // accelerator interface @@ -102,6 +112,14 @@ module idma_inst64_top #( axi_req_t [NumChannels-1:0] axi_read_req, axi_write_req; axi_res_t [NumChannels-1:0] axi_read_rsp, axi_write_rsp; + // internal Init channels + init_req_t [NumChannels-1:0] init_read_req, init_write_req; + init_res_t [NumChannels-1:0] init_read_rsp, init_write_rsp; + + // internal OBI channels + obi_req_t [NumChannels-1:0] obi_read_req, obi_write_req; + obi_res_t [NumChannels-1:0] obi_read_rsp, obi_write_rsp; + // backend signals idma_req_t [NumChannels-1:0] idma_req; logic [NumChannels-1:0] idma_req_valid; @@ -149,7 +167,7 @@ module idma_inst64_top #( // Backend instantiation //-------------------------------------- for (genvar c = 0; c < NumChannels; c++) begin : gen_backend - idma_backend_rw_axi #( + idma_backend_rw_axi_rw_init_rw_obi #( .DataWidth ( AxiDataWidth ), .AddrWidth ( AxiAddrWidth ), .UserWidth ( AxiUserWidth ), @@ -171,41 +189,53 @@ module idma_inst64_top #( .idma_busy_t ( idma_pkg::idma_busy_t ), .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_res_t ), + .init_req_t ( init_req_t ), + .init_rsp_t ( init_res_t ), + .obi_req_t ( obi_req_t ), + .obi_rsp_t ( obi_res_t ), .read_meta_channel_t ( read_meta_channel_t ), .write_meta_channel_t ( write_meta_channel_t ) - ) i_idma_backend_rw_axi ( + ) i_idma_backend_rw_axi_rw_init_rw_obi ( .clk_i, .rst_ni, .testmode_i, - .idma_req_i ( idma_req [c] ), - .req_valid_i ( idma_req_valid [c] ), - .req_ready_o ( idma_req_ready [c] ), - .idma_rsp_o ( idma_rsp [c] ), - .rsp_valid_o ( idma_rsp_valid [c] ), - .rsp_ready_i ( idma_rsp_ready [c] ), - .idma_eh_req_i ( '0 ), - .eh_req_valid_i ( 1'b0 ), - .eh_req_ready_o ( /* NC */ ), - .axi_read_req_o ( axi_read_req [c] ), - .axi_read_rsp_i ( axi_read_rsp [c] ), - .axi_write_req_o ( axi_write_req [c] ), - .axi_write_rsp_i ( axi_write_rsp [c] ), - .busy_o ( idma_busy [c] ) + .idma_req_i ( idma_req [c] ), + .req_valid_i ( idma_req_valid [c] ), + .req_ready_o ( idma_req_ready [c] ), + .idma_rsp_o ( idma_rsp [c] ), + .rsp_valid_o ( idma_rsp_valid [c] ), + .rsp_ready_i ( idma_rsp_ready [c] ), + .idma_eh_req_i ( '0 ), + .eh_req_valid_i ( 1'b0 ), + .eh_req_ready_o ( /* NC */ ), + .axi_read_req_o ( axi_read_req [c] ), + .axi_read_rsp_i ( axi_read_rsp [c] ), + .init_read_req_o ( init_read_req [c] ), + .init_read_rsp_i ( init_read_rsp [c] ), + .obi_read_req_o ( obi_read_req [c] ), + .obi_read_rsp_i ( obi_read_rsp [c] ), + .axi_write_req_o ( axi_write_req [c] ), + .axi_write_rsp_i ( axi_write_rsp [c] ), + .init_write_req_o ( init_write_req [c] ), + .init_write_rsp_i ( init_write_rsp [c] ), + .obi_write_req_o ( obi_write_req [c] ), + .obi_write_rsp_i ( obi_write_rsp [c] ), + .busy_o ( idma_busy [c] ) ); - axi_rw_join #( - .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_res_t ) - ) i_axi_rw_join ( - .clk_i, - .rst_ni, - .slv_read_req_i ( axi_read_req [c] ), - .slv_read_resp_o ( axi_read_rsp [c] ), - .slv_write_req_i ( axi_write_req [c] ), - .slv_write_resp_o ( axi_write_rsp [c] ), - .mst_req_o ( axi_req_o [c] ), - .mst_resp_i ( axi_res_i [c] ) - ); + // axi_rw_join #( + // .axi_req_t ( axi_req_t ), + // .axi_resp_t ( axi_res_t ) + // ) i_axi_rw_join ( + // .clk_i, + // .rst_ni, + // .slv_read_req_i ( axi_read_req [c] ), + // .slv_read_resp_o ( axi_read_rsp [c] ), + // .slv_write_req_i ( axi_write_req [c] ), + // .slv_write_resp_o ( axi_write_rsp [c] ), + // .mst_req_o ( axi_req_o [c] ), + // .mst_resp_i ( axi_res_i [c] ) + // ); assign busy_o[c] = (|idma_busy[c]) | idma_nd_busy[c]; end From 83fd7165f3703d0aff5382dc5a6119945ad409ff Mon Sep 17 00:00:00 2001 From: "msc24h31 Lucia Luzi (luzil)" Date: Thu, 12 Dec 2024 20:51:17 +0100 Subject: [PATCH 04/18] frontend: larger reorder buffer --- src/frontend/inst64/idma_inst64_top.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/frontend/inst64/idma_inst64_top.sv b/src/frontend/inst64/idma_inst64_top.sv index f27cb79c..83fea0f3 100644 --- a/src/frontend/inst64/idma_inst64_top.sv +++ b/src/frontend/inst64/idma_inst64_top.sv @@ -65,7 +65,7 @@ module idma_inst64_top #( localparam int unsigned TFLenWidth = AxiAddrWidth; localparam int unsigned RepWidth = 32'd32; localparam int unsigned NumDim = 32'd2; - localparam int unsigned BufferDepth = 32'd3; + localparam int unsigned BufferDepth = 32'd16; // derived constants and types localparam int unsigned StrbWidth = AxiDataWidth / 32'd8; @@ -452,7 +452,7 @@ module idma_inst64_top #( // 4. send acc response (pvalid) // 5. acknowledge acc request (qready) if (acc_res_ready) begin - idma_fe_req_valid [idma_fe_sel_chan] = 1'b1; + idma_fe_req_valid[idma_fe_sel_chan] = 1'b1; if (idma_fe_req_ready[idma_fe_sel_chan]) begin acc_res.id = acc_req_i.id; acc_res.data = next_id[idma_fe_sel_chan]; From 29bab4585e10dbb79a0bc44181abb9dda3697a91 Mon Sep 17 00:00:00 2001 From: "msc24h31 Lucia Luzi (luzil)" Date: Fri, 13 Dec 2024 12:06:41 +0100 Subject: [PATCH 05/18] frontend: increase BufferDepth --- src/frontend/inst64/idma_inst64_top.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/frontend/inst64/idma_inst64_top.sv b/src/frontend/inst64/idma_inst64_top.sv index 83fea0f3..eaa57166 100644 --- a/src/frontend/inst64/idma_inst64_top.sv +++ b/src/frontend/inst64/idma_inst64_top.sv @@ -65,7 +65,7 @@ module idma_inst64_top #( localparam int unsigned TFLenWidth = AxiAddrWidth; localparam int unsigned RepWidth = 32'd32; localparam int unsigned NumDim = 32'd2; - localparam int unsigned BufferDepth = 32'd16; + localparam int unsigned BufferDepth = 32'd64; // derived constants and types localparam int unsigned StrbWidth = AxiDataWidth / 32'd8; From b3516ba53d18e6eea0e5cf426da617f87fa7c9f4 Mon Sep 17 00:00:00 2001 From: "msc24h31 Lucia Luzi (luzil)" Date: Mon, 9 Dec 2024 15:28:51 +0100 Subject: [PATCH 06/18] gitignore add modelsim.ini --- .gitignore | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index f0b54d46..19af7750 100644 --- a/.gitignore +++ b/.gitignore @@ -11,4 +11,5 @@ working_dir bender morty todo -.venv \ No newline at end of file +.venv +modelsim.ini \ No newline at end of file From 63192c8fbae7a9f2348de326af2b4b84773e7a93 Mon Sep 17 00:00:00 2001 From: "msc24h31 Lucia Luzi (luzil)" Date: Sun, 22 Dec 2024 23:13:13 +0100 Subject: [PATCH 07/18] frontend: address decoder first draft --- src/frontend/inst64/idma_inst64_top.sv | 62 +++++++++++++++++++++++++- 1 file changed, 60 insertions(+), 2 deletions(-) diff --git a/src/frontend/inst64/idma_inst64_top.sv b/src/frontend/inst64/idma_inst64_top.sv index eaa57166..fc35d8c8 100644 --- a/src/frontend/inst64/idma_inst64_top.sv +++ b/src/frontend/inst64/idma_inst64_top.sv @@ -30,7 +30,9 @@ module idma_inst64_top #( parameter type obi_res_t = logic, parameter type acc_req_t = logic, parameter type acc_res_t = logic, - parameter type dma_events_t = logic + parameter type dma_events_t = logic, + parameter axi_pkg::xbar_cfg_t Cfg = '0, + parameter type addr_rule_t = axi_pkg::xbar_rule_64_t ) ( input logic clk_i, input logic rst_ni, @@ -57,7 +59,9 @@ module idma_inst64_top #( // hart id of the frankensnitch input logic [31:0] hart_id_i, // performance output - output dma_events_t [NumChannels-1:0] events_o + output dma_events_t [NumChannels-1:0] events_o, + // address decode map + input rule_t [Cfg.NoAddrRules-1:0] addr_map_i ); // constants @@ -349,6 +353,60 @@ module idma_inst64_top #( .data_o ( acc_res_o ) ); + //-------------------------------------- + // Address decode + //-------------------------------------- + logic [Cfg.NoSlvPorts-1:0][$clog2(Cfg.NoMstPorts)-1:0] default_port; + localparam bit EnableDefaultMstPort = 1'b1; + assign default_port = '{default: SoCDMAOut}; + // address decoder for write address / source address + addr_decode #( + .NoIndices ( Cfg.NoMstPorts ), + .NoRules ( Cfg.NoAddrRules ), + .addr_t ( addr_t ), + .rule_t ( rule_t ) + ) i_idma_aw_decode ( + .addr_i ( idma_fe_req_d.burst_req.src_addr[AxiAddrWidth-1:0] ), + .addr_map_i ( addr_map_i ), + .idx_o ( idx_aw ), + .dec_valid_o ( idx_aw_valid ), + .dec_error_o ( idx_aw_error ), + .en_default_idx_i ( '1 ), + .default_idx_i ( default_port[0] ) + ); + // address decoder for read address / destination address + addr_decode #( + .NoIndices ( Cfg.NoMstPorts ), + .addr_t ( addr_t ), + .NoRules ( Cfg.NoAddrRules ), + .rule_t ( rule_t ) + ) i_idma_ar_decode ( + .addr_i ( idma_fe_req_d.burst_req.dst_addr[AxiAddrWidth-1:0] ), + .addr_map_i ( addr_map_i ), + .idx_o ( idx_ar ), + .dec_valid_o ( idx_ar_valid ), + .dec_error_o ( idx_ar_error ), + .en_default_idx_i ( EnableDefaultMstPort ), + .default_idx_i ( default_port[0] ) + ); + //TODO: rename signals + assign slv_aw_select = (idx_aw_error) ? + mst_port_idx_t'(Cfg.NoMstPorts) : mst_port_idx_t'(idx_aw); + assign slv_ar_select = (idx_ar_error) ? + mst_port_idx_t'(Cfg.NoMstPorts) : mst_port_idx_t'(idx_ar); + + unique casez (slv_aw_select) + TCDMDMA : begin + idma_fe_req_d.burst_req.opt.src_protocol = idma_pkg::OBI; + + end + ZeroMemory : begin + idma_fe_req_d.burst_req.opt.src_protocol = idma_pkg::INIT; + end + SoCDMAOut : begin + idma_fe_req_d.burst_req.opt.src_protocol = idma_pkg::AXI; + end + endcase //-------------------------------------- // Instruction decode From 5e4ed92c095ef50911c19701ed50bbd847ed6201 Mon Sep 17 00:00:00 2001 From: Lucia Luzi Date: Wed, 15 Jan 2025 14:54:32 +0100 Subject: [PATCH 08/18] frontend: small changes to address decoder --- src/frontend/inst64/idma_inst64_top.sv | 50 +++++++++++++------------- 1 file changed, 26 insertions(+), 24 deletions(-) diff --git a/src/frontend/inst64/idma_inst64_top.sv b/src/frontend/inst64/idma_inst64_top.sv index fc35d8c8..5b7a8944 100644 --- a/src/frontend/inst64/idma_inst64_top.sv +++ b/src/frontend/inst64/idma_inst64_top.sv @@ -356,49 +356,51 @@ module idma_inst64_top #( //-------------------------------------- // Address decode //-------------------------------------- - logic [Cfg.NoSlvPorts-1:0][$clog2(Cfg.NoMstPorts)-1:0] default_port; - localparam bit EnableDefaultMstPort = 1'b1; - assign default_port = '{default: SoCDMAOut}; - // address decoder for write address / source address + // logic [Cfg.NoSlvPorts-1:0][$clog2(Cfg.NoMstPorts)-1:0] default_port; + // localparam bit EnableDefaultMstPort = 1'b1; + // assign default_port = '{default: SoCDMAOut}; + + // address decoder for source address + // if (opt.beo.init_set) + // src_protocol = INIT addr_decode #( .NoIndices ( Cfg.NoMstPorts ), .NoRules ( Cfg.NoAddrRules ), .addr_t ( addr_t ), .rule_t ( rule_t ) - ) i_idma_aw_decode ( + ) i_idma_src_decode ( .addr_i ( idma_fe_req_d.burst_req.src_addr[AxiAddrWidth-1:0] ), .addr_map_i ( addr_map_i ), - .idx_o ( idx_aw ), - .dec_valid_o ( idx_aw_valid ), - .dec_error_o ( idx_aw_error ), - .en_default_idx_i ( '1 ), - .default_idx_i ( default_port[0] ) + .idx_o ( idx_src ), + .dec_valid_o ( idx_src_valid ), + .dec_error_o ( idx_src_error ), + .en_default_idx_i ( 1'b1 ), + .default_idx_i ( SoCDMAOut ) ); - // address decoder for read address / destination address + // address decoder for destination address addr_decode #( .NoIndices ( Cfg.NoMstPorts ), .addr_t ( addr_t ), .NoRules ( Cfg.NoAddrRules ), .rule_t ( rule_t ) - ) i_idma_ar_decode ( + ) i_idma_dst_decode ( .addr_i ( idma_fe_req_d.burst_req.dst_addr[AxiAddrWidth-1:0] ), .addr_map_i ( addr_map_i ), - .idx_o ( idx_ar ), - .dec_valid_o ( idx_ar_valid ), - .dec_error_o ( idx_ar_error ), - .en_default_idx_i ( EnableDefaultMstPort ), - .default_idx_i ( default_port[0] ) + .idx_o ( idx_dst ), + .dec_valid_o ( idx_dst_valid ), + .dec_error_o ( idx_dst_error ), + .en_default_idx_i ( 1'b1 ), + .default_idx_i ( SoCDMAOut ) ); - //TODO: rename signals - assign slv_aw_select = (idx_aw_error) ? - mst_port_idx_t'(Cfg.NoMstPorts) : mst_port_idx_t'(idx_aw); - assign slv_ar_select = (idx_ar_error) ? - mst_port_idx_t'(Cfg.NoMstPorts) : mst_port_idx_t'(idx_ar); - unique casez (slv_aw_select) + assign src_select = (idx_src_error) ? + mst_port_idx_t'(Cfg.NoMstPorts) : mst_port_idx_t'(idx_src); + assign ar_select = (idx_dst_error) ? + mst_port_idx_t'(Cfg.NoMstPorts) : mst_port_idx_t'(idx_dst); + + unique casez (src_select) TCDMDMA : begin idma_fe_req_d.burst_req.opt.src_protocol = idma_pkg::OBI; - end ZeroMemory : begin idma_fe_req_d.burst_req.opt.src_protocol = idma_pkg::INIT; From 7b7c2e056fe2e85607a9cc725752954965b0e801 Mon Sep 17 00:00:00 2001 From: Lucia Luzi Date: Sun, 19 Jan 2025 18:28:50 +0100 Subject: [PATCH 09/18] frontend: add DMINIT instr encoding --- src/frontend/inst64/idma_inst64_snitch_pkg.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/src/frontend/inst64/idma_inst64_snitch_pkg.sv b/src/frontend/inst64/idma_inst64_snitch_pkg.sv index a3cc8e88..ca3c6ea0 100644 --- a/src/frontend/inst64/idma_inst64_snitch_pkg.sv +++ b/src/frontend/inst64/idma_inst64_snitch_pkg.sv @@ -17,5 +17,6 @@ package idma_inst64_snitch_pkg; localparam logic [31:0] DMSTAT = 32'b0000101?????00000000?????0101011; localparam logic [31:0] DMSTR = 32'b0000110??????????000000000101011; localparam logic [31:0] DMREP = 32'b000011100000?????000000000101011; + localparam logic [31:0] DMINIT = 32'b0001000??????????000?????0101011; endpackage From e25f9b8965803dc6d9d0f5c99299f6b26df755ab Mon Sep 17 00:00:00 2001 From: Lucia Luzi Date: Thu, 30 Jan 2025 12:54:01 +0100 Subject: [PATCH 10/18] frontend: changes to init & obi signals - move address decoder into instr decoder - add INIT setup with spill register - add mux/demux for OBI req/rsp - fix typo in init_rsp_t --- Bender.lock | 20 +- src/frontend/inst64/idma_inst64_top.sv | 244 ++++++++++++++++++------- 2 files changed, 188 insertions(+), 76 deletions(-) diff --git a/Bender.lock b/Bender.lock index 9f1098b1..5c9475bf 100644 --- a/Bender.lock +++ b/Bender.lock @@ -7,8 +7,8 @@ packages: dependencies: - common_cells axi: - revision: fccffb5953ec8564218ba05e20adbedec845e014 - version: 0.39.1 + revision: 39f5f2d51c5e524f6fc5cf8b6e901f7dcc5622d7 + version: 0.39.6 source: Git: https://github.com/pulp-platform/axi.git dependencies: @@ -23,30 +23,30 @@ packages: dependencies: - common_cells common_cells: - revision: 13f28aa0021fc22c0d01a12d618fda58d2c93239 - version: 1.33.0 + revision: c27bce39ebb2e6bae52f60960814a2afca7bd4cb + version: 1.37.0 source: Git: https://github.com/pulp-platform/common_cells.git dependencies: - common_verification - tech_cells_generic common_verification: - revision: 9c07fa860593b2caabd9b5681740c25fac04b878 - version: 0.2.3 + revision: fb1885f48ea46164a10568aeff51884389f67ae3 + version: 0.2.5 source: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] obi: - revision: 1aa411df145c4ebdd61f8fed4d003c33f7b20636 - version: 0.1.2 + revision: 5321106817e177d6c16ecc4daa922b96b1bc946b + version: 0.1.5 source: Git: https://github.com/pulp-platform/obi.git dependencies: - common_cells - common_verification register_interface: - revision: e25b36670ff7aab3402f40efcc2b11ee0f31cf19 - version: 0.4.3 + revision: 5daa85d164cf6b54ad061ea1e4c6f3624556e467 + version: 0.4.5 source: Git: https://github.com/pulp-platform/register_interface.git dependencies: diff --git a/src/frontend/inst64/idma_inst64_top.sv b/src/frontend/inst64/idma_inst64_top.sv index 5b7a8944..c38ba689 100644 --- a/src/frontend/inst64/idma_inst64_top.sv +++ b/src/frontend/inst64/idma_inst64_top.sv @@ -31,7 +31,6 @@ module idma_inst64_top #( parameter type acc_req_t = logic, parameter type acc_res_t = logic, parameter type dma_events_t = logic, - parameter axi_pkg::xbar_cfg_t Cfg = '0, parameter type addr_rule_t = axi_pkg::xbar_rule_64_t ) ( input logic clk_i, @@ -42,7 +41,7 @@ module idma_inst64_top #( input axi_res_t [NumChannels-1:0] axi_res_i, // Memory Init output init_req_t [NumChannels-1:0] init_req_o, - input init_res_t [NumChannels-1:0] init_res_i, + input init_rsp_t [NumChannels-1:0] init_res_i, // OBI interconnect output obi_req_t [NumChannels-1:0] obi_req_o, input obi_res_t [NumChannels-1:0] obi_res_i, @@ -61,7 +60,7 @@ module idma_inst64_top #( // performance output output dma_events_t [NumChannels-1:0] events_o, // address decode map - input rule_t [Cfg.NoAddrRules-1:0] addr_map_i + input addr_rule_t [Cfg.NoAddrRules-1:0] addr_map_i ); // constants @@ -70,6 +69,7 @@ module idma_inst64_top #( localparam int unsigned RepWidth = 32'd32; localparam int unsigned NumDim = 32'd2; localparam int unsigned BufferDepth = 32'd64; + localparam int unsigned NumRules = 32'd4; // derived constants and types localparam int unsigned StrbWidth = AxiDataWidth / 32'd8; @@ -118,11 +118,13 @@ module idma_inst64_top #( // internal Init channels init_req_t [NumChannels-1:0] init_read_req, init_write_req; - init_res_t [NumChannels-1:0] init_read_rsp, init_write_rsp; + init_rsp_t [NumChannels-1:0] init_read_rsp, init_write_rsp; + logic [7:0] init_read_rsp_byte; // internal OBI channels obi_req_t [NumChannels-1:0] obi_read_req, obi_write_req; obi_res_t [NumChannels-1:0] obi_read_rsp, obi_write_rsp; + logic [NumChannels-1:0] obi_we_q, obi_we_d; // backend signals idma_req_t [NumChannels-1:0] idma_req; @@ -147,6 +149,7 @@ module idma_inst64_top #( // frontend state logic [1:0] idma_fe_cfg; + logic [1:0] idma_fe_init_cfg; logic [1:0] idma_fe_status; logic [2:0] idma_fe_sel_chan; logic idma_fe_twod; @@ -166,6 +169,13 @@ module idma_inst64_top #( logic acc_res_valid; logic acc_res_ready; + // decoder signals + logic [NumRules-1:0] idx_src; + logic idx_src_valid; + logic idx_src_error; + logic [NumRules-1:0] idx_dst; + logic idx_dst_valid; + logic idx_dst_error; //-------------------------------------- // Backend instantiation @@ -194,7 +204,7 @@ module idma_inst64_top #( .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_res_t ), .init_req_t ( init_req_t ), - .init_rsp_t ( init_res_t ), + .init_rsp_t ( init_rsp_t ), .obi_req_t ( obi_req_t ), .obi_rsp_t ( obi_res_t ), .read_meta_channel_t ( read_meta_channel_t ), @@ -227,19 +237,64 @@ module idma_inst64_top #( .busy_o ( idma_busy [c] ) ); - // axi_rw_join #( - // .axi_req_t ( axi_req_t ), - // .axi_resp_t ( axi_res_t ) - // ) i_axi_rw_join ( - // .clk_i, - // .rst_ni, - // .slv_read_req_i ( axi_read_req [c] ), - // .slv_read_resp_o ( axi_read_rsp [c] ), - // .slv_write_req_i ( axi_write_req [c] ), - // .slv_write_resp_o ( axi_write_rsp [c] ), - // .mst_req_o ( axi_req_o [c] ), - // .mst_resp_i ( axi_res_i [c] ) - // ); + axi_rw_join #( + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_res_t ) + ) i_axi_rw_join ( + .clk_i, + .rst_ni, + .slv_read_req_i ( axi_read_req [c] ), + .slv_read_resp_o ( axi_read_rsp [c] ), + .slv_write_req_i ( axi_write_req [c] ), + .slv_write_resp_o ( axi_write_rsp [c] ), + .mst_req_o ( axi_req_o [c] ), + .mst_resp_i ( axi_res_i [c] ) + ); + + // INIT setup + spill_register #( + .T ( init_req_t ) + ) i_spill_register_init ( + .clk_i, + .rst_ni, + .valid_i ( init_read_req[c].req_valid ), + .ready_o ( init_read_rsp[c].req_ready ), + .data_i ( init_read_req[c].req_chan.cfg[7:0] ), + .valid_o ( init_read_rsp[c].rsp_valid ), + .ready_i ( init_read_req[c].rsp_ready ), + .data_o ( init_read_rsp_byte ) + ); + + assign init_read_rsp[c].rsp_chan.init = {{StrbWidth}{init_read_rsp_byte}}; + + // OBI mux read or write + assign obi_we_q[c] = obi_write_req[c].a.we; + `FF(obi_we_q[c], obi_we_d[c], '0) + + stream_mux #( + .DATA_T ( obi_req_t ), + .N_INP ( 32'd2 ) + ) i_obi_rw_mux ( + .inp_data_i ( {obi_write_req[c], obi_read_req[c] } ), + .inp_valid_i ( {(obi_write_req[c] != '0), (obi_read_req[c] != '0)} ), + .inp_ready_o ( {obi_write_rsp[c].gnt, obi_read_rsp[c].gnt } ), + .inp_sel_i ( obi_write_req[c].a.we ), + .oup_data_o ( obi_req_o[c] ), + .oup_valid_o ( ), + .oup_ready_i ( obi_res_i[c].gnt ) + ); + + stream_demux #( + .DATA_T ( obi_res_t ), + .N_OUP ( 32'd2 ) + ) i_stream_demux ( + .inp_valid_i ( obi_res_i[c].rvalid ), + .inp_ready_o ( obi_req_o[c].rready ), + .oup_sel_i ( obi_we_d[c] ), + .oup_valid_o ( {obi_write_res[c].rvalid , obi_read_res[c].rvalid } ), + .oup_ready_i ( {obi_write_req[c].rready , obi_read_req[c].rready } ) + ); + assign busy_o[c] = (|idma_busy[c]) | idma_nd_busy[c]; end @@ -353,62 +408,37 @@ module idma_inst64_top #( .data_o ( acc_res_o ) ); - //-------------------------------------- - // Address decode - //-------------------------------------- - // logic [Cfg.NoSlvPorts-1:0][$clog2(Cfg.NoMstPorts)-1:0] default_port; - // localparam bit EnableDefaultMstPort = 1'b1; - // assign default_port = '{default: SoCDMAOut}; - - // address decoder for source address - // if (opt.beo.init_set) - // src_protocol = INIT + // Address Decode addr_decode #( - .NoIndices ( Cfg.NoMstPorts ), - .NoRules ( Cfg.NoAddrRules ), - .addr_t ( addr_t ), - .rule_t ( rule_t ) + .NoIndices ( 32'd2 ), + .NoRules ( 32'd2 ), + .addr_t ( addr_t ), + .rule_t ( addr_rule_t ) ) i_idma_src_decode ( - .addr_i ( idma_fe_req_d.burst_req.src_addr[AxiAddrWidth-1:0] ), - .addr_map_i ( addr_map_i ), - .idx_o ( idx_src ), - .dec_valid_o ( idx_src_valid ), - .dec_error_o ( idx_src_error ), - .en_default_idx_i ( 1'b1 ), - .default_idx_i ( SoCDMAOut ) + .addr_i ( idma_fe_req_d.burst_req.src_addr[AxiAddrWidth-1:0] ), + .addr_map_i ( addr_map_i ), + .idx_o ( idx_src ), + .dec_valid_o ( idx_src_valid ), + .dec_error_o ( idx_src_error ), + .en_default_idx_i ( 1'b1 ), + .default_idx_i ( 32'd4 ) ); // address decoder for destination address addr_decode #( - .NoIndices ( Cfg.NoMstPorts ), - .addr_t ( addr_t ), - .NoRules ( Cfg.NoAddrRules ), - .rule_t ( rule_t ) + .NoIndices ( 32'd2 ), + .addr_t ( addr_t ), + .NoRules ( 32'd2 ), + .rule_t ( addr_rule_t ) ) i_idma_dst_decode ( - .addr_i ( idma_fe_req_d.burst_req.dst_addr[AxiAddrWidth-1:0] ), - .addr_map_i ( addr_map_i ), - .idx_o ( idx_dst ), - .dec_valid_o ( idx_dst_valid ), - .dec_error_o ( idx_dst_error ), - .en_default_idx_i ( 1'b1 ), - .default_idx_i ( SoCDMAOut ) + .addr_i ( idma_fe_req_d.burst_req.dst_addr[AxiAddrWidth-1:0] ), + .addr_map_i ( addr_map_i ), + .idx_o ( idx_dst ), + .dec_valid_o ( idx_dst_valid ), + .dec_error_o ( idx_dst_error ), + .en_default_idx_i ( 1'b1 ), + .default_idx_i ( 32'd4 ) ); - assign src_select = (idx_src_error) ? - mst_port_idx_t'(Cfg.NoMstPorts) : mst_port_idx_t'(idx_src); - assign ar_select = (idx_dst_error) ? - mst_port_idx_t'(Cfg.NoMstPorts) : mst_port_idx_t'(idx_dst); - - unique casez (src_select) - TCDMDMA : begin - idma_fe_req_d.burst_req.opt.src_protocol = idma_pkg::OBI; - end - ZeroMemory : begin - idma_fe_req_d.burst_req.opt.src_protocol = idma_pkg::INIT; - end - SoCDMAOut : begin - idma_fe_req_d.burst_req.opt.src_protocol = idma_pkg::AXI; - end - endcase //-------------------------------------- // Instruction decode @@ -523,6 +553,55 @@ module idma_inst64_top #( end end + // use init for memset + idma_inst64_snitch_pkg::DMINIT : begin + // Parse the transfer parameters from the register or immediate. + unique casez (acc_req_i.data_op) + idma_inst64_snitch_pkg::DMINIT : begin + idma_fe_init_cfg = acc_req_i.data_op[21:20]; + idma_fe_sel_chan = acc_req_i.data_op[24:22]; + end + default:; + endcase + + dma_op_name = "DMINIT"; + is_dma_op = 1'b1; + idma_fe_req_d.burst_req.opt.axi_id = idma_fe_sel_chan; + idma_fe_req_d.burst_req.length = acc_req_i.data_arga; + idma_fe_req_d.burst_req.opt.src_protocol = idma_pkg::INIT; + idma_fe_req_d.burst_req.opt.dst_protocol = idma_pkg::INIT; + + // save correct value as src addr, depending on cfg + case (idma_fe_init_cfg) + 2'b00 : idma_fe_req_d.burst_req.src_addr[AxiAddrWidth-1:0] = 0; + 2'b01 : idma_fe_req_d.burst_req.src_addr[AxiAddrWidth-1:0] = 'b11111111; + // else: DMSRC already added the value to idma_fe_req_d.burst_req.src_addr[AxiAddrWidth-1:0] + endcase + + // set strides and reps + // 1 byte value is repeated 'size' times + idma_fe_req_d.d_req[0].src_strides = 0; + idma_fe_req_d.d_req[0].dst_strides = 1'b1; + idma_fe_req_d.d_req[0].reps = acc_req_i.data_arga; + + // Perform the following sequence: + // 1. wait for acc response channel to be ready (pready) + // 2. request twod transfer (valid) + // 3. wait for twod transfer to be accepted (ready) + // 4. send acc response (pvalid) + // 5. acknowledge acc request (qready) + if (acc_res_ready) begin + idma_fe_req_valid[idma_fe_sel_chan] = 1'b1; + if (idma_fe_req_ready[idma_fe_sel_chan]) begin + acc_res.id = acc_req_i.id; + acc_res.data = next_id[idma_fe_sel_chan]; + acc_res.error = 1'b0; + acc_res_valid = 1'b1; + acc_req_ready_o = idma_fe_req_ready[idma_fe_sel_chan]; + end + end + end + // status of the DMA idma_inst64_snitch_pkg::DMSTATI, idma_inst64_snitch_pkg::DMSTAT: begin @@ -581,6 +660,39 @@ module idma_inst64_top #( default:; endcase end + + //---------------- + // Address decode + //---------------- + + if (idma_fe_req_d.burst_req.opt.src_protocol != idma_pkg::INIT) begin + + assign idx_src = (idx_src_error) ? 32'd4 : (idx_src); + assign idx_dst = (idx_dst_error) ? 32'd4 : (idx_dst); + + + unique casez (idx_src) + 32'd0, 32'd2: begin //TCDM + idma_fe_req_d.burst_req.opt.src_protocol = idma_pkg::OBI; + end + 32'd1, 32'd3 : begin //ZeroMem + end + default : begin //SoCDMAOut + idma_fe_req_d.burst_req.opt.src_protocol = idma_pkg::AXI; + end + endcase + unique casez (idx_dst) + 32'd0, 32'd2: begin //TCDM + idma_fe_req_d.burst_req.opt.dst_protocol = idma_pkg::OBI; + end + 32'd1, 32'd3 : begin //ZeroMem + end + default : begin //SoCDMAOut + idma_fe_req_d.burst_req.opt.dst_protocol = idma_pkg::AXI; + end + endcase + end + end // twod handling From 7a4e9162c15355d964e2cee573826be581a22f05 Mon Sep 17 00:00:00 2001 From: Lucia Luzi Date: Fri, 31 Jan 2025 16:15:11 +0100 Subject: [PATCH 11/18] frontend: fix small typos --- src/frontend/inst64/idma_inst64_top.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/frontend/inst64/idma_inst64_top.sv b/src/frontend/inst64/idma_inst64_top.sv index c38ba689..66aa8658 100644 --- a/src/frontend/inst64/idma_inst64_top.sv +++ b/src/frontend/inst64/idma_inst64_top.sv @@ -60,7 +60,7 @@ module idma_inst64_top #( // performance output output dma_events_t [NumChannels-1:0] events_o, // address decode map - input addr_rule_t [Cfg.NoAddrRules-1:0] addr_map_i + input addr_rule_t [3:0] addr_map_i ); // constants @@ -291,7 +291,7 @@ module idma_inst64_top #( .inp_valid_i ( obi_res_i[c].rvalid ), .inp_ready_o ( obi_req_o[c].rready ), .oup_sel_i ( obi_we_d[c] ), - .oup_valid_o ( {obi_write_res[c].rvalid , obi_read_res[c].rvalid } ), + .oup_valid_o ( {obi_write_rsp[c].rvalid , obi_read_rsp[c].rvalid } ), .oup_ready_i ( {obi_write_req[c].rready , obi_read_req[c].rready } ) ); From 7bf0d2bd5af4cb5dc3b2495950b9470a689fb2b9 Mon Sep 17 00:00:00 2001 From: Lucia Luzi Date: Fri, 31 Jan 2025 17:19:25 +0100 Subject: [PATCH 12/18] frontend: add obi & init (meta) channels --- src/frontend/inst64/idma_inst64_top.sv | 31 ++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/src/frontend/inst64/idma_inst64_top.sv b/src/frontend/inst64/idma_inst64_top.sv index 66aa8658..b7fe67fa 100644 --- a/src/frontend/inst64/idma_inst64_top.sv +++ b/src/frontend/inst64/idma_inst64_top.sv @@ -24,8 +24,12 @@ module idma_inst64_top #( parameter type axi_aw_chan_t = logic, parameter type axi_req_t = logic, parameter type axi_res_t = logic, + parameter type init_req_chan_t = logic, + parameter type init_rsp_chan_t = logic, parameter type init_req_t = logic, parameter type init_rsp_t = logic, + parameter type obi_a_chan_t = logic, + parameter type obi_r_chan_t = logic, parameter type obi_req_t = logic, parameter type obi_res_t = logic, parameter type acc_req_t = logic, @@ -101,7 +105,17 @@ module idma_inst64_top #( } axi_read_meta_channel_t; typedef struct packed { - axi_read_meta_channel_t axi; + obi_a_chan_t a_chan; + } obi_read_meta_channel_t; + + typedef struct packed { + init_req_chan_t req_chan; + } init_read_meta_channel_t; + + typedef struct packed { + axi_read_meta_channel_t axi; + obi_read_meta_channel_t obi; + init_read_meta_channel_t init; } read_meta_channel_t; typedef struct packed { @@ -109,7 +123,17 @@ module idma_inst64_top #( } axi_write_meta_channel_t; typedef struct packed { - axi_write_meta_channel_t axi; + obi_a_chan_t a_chan; + } obi_write_meta_channel_t; + + typedef struct packed { + init_req_chan_t req_chan; + } init_write_meta_channel_t; + + typedef struct packed { + axi_write_meta_channel_t axi; + obi_write_meta_channel_t obi; + init_write_meta_channel_t init; } write_meta_channel_t; // internal AXI channels @@ -285,7 +309,6 @@ module idma_inst64_top #( ); stream_demux #( - .DATA_T ( obi_res_t ), .N_OUP ( 32'd2 ) ) i_stream_demux ( .inp_valid_i ( obi_res_i[c].rvalid ), @@ -730,7 +753,7 @@ module idma_inst64_top #( $sformat(trace_file, "dma_trace_%05x_%05x.log", hart_id_i, c); end // attach the tracer - `IDMA_TRACER_RW_AXI(gen_backend[c].i_idma_backend_rw_axi, trace_file); + `IDMA_TRACER_RW_AXI(gen_backend[c].i_idma_backend_rw_axi_rw_init_rw_obi, trace_file); end end `endif From 6ba2002e5273c360c04b0a25d3da8bbbef59907e Mon Sep 17 00:00:00 2001 From: Lucia Luzi Date: Mon, 3 Feb 2025 15:13:00 +0100 Subject: [PATCH 13/18] frontend: fix typo in obi_we_q --- src/frontend/inst64/idma_inst64_top.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/frontend/inst64/idma_inst64_top.sv b/src/frontend/inst64/idma_inst64_top.sv index b7fe67fa..02d5c516 100644 --- a/src/frontend/inst64/idma_inst64_top.sv +++ b/src/frontend/inst64/idma_inst64_top.sv @@ -292,8 +292,8 @@ module idma_inst64_top #( assign init_read_rsp[c].rsp_chan.init = {{StrbWidth}{init_read_rsp_byte}}; // OBI mux read or write - assign obi_we_q[c] = obi_write_req[c].a.we; - `FF(obi_we_q[c], obi_we_d[c], '0) + assign obi_we_d[c] = obi_write_req[c].a.we; + `FF(obi_we_q[c], obi_we_d[c], '0, clk_i, rst_ni) stream_mux #( .DATA_T ( obi_req_t ), @@ -302,7 +302,7 @@ module idma_inst64_top #( .inp_data_i ( {obi_write_req[c], obi_read_req[c] } ), .inp_valid_i ( {(obi_write_req[c] != '0), (obi_read_req[c] != '0)} ), .inp_ready_o ( {obi_write_rsp[c].gnt, obi_read_rsp[c].gnt } ), - .inp_sel_i ( obi_write_req[c].a.we ), + .inp_sel_i ( obi_we_d[c] ), .oup_data_o ( obi_req_o[c] ), .oup_valid_o ( ), .oup_ready_i ( obi_res_i[c].gnt ) @@ -313,7 +313,7 @@ module idma_inst64_top #( ) i_stream_demux ( .inp_valid_i ( obi_res_i[c].rvalid ), .inp_ready_o ( obi_req_o[c].rready ), - .oup_sel_i ( obi_we_d[c] ), + .oup_sel_i ( obi_we_q[c] ), .oup_valid_o ( {obi_write_rsp[c].rvalid , obi_read_rsp[c].rvalid } ), .oup_ready_i ( {obi_write_req[c].rready , obi_read_req[c].rready } ) ); From cc100af9a7945970b3f6335ad1da70c77572794a Mon Sep 17 00:00:00 2001 From: Lucia Luzi Date: Tue, 4 Feb 2025 14:32:13 +0100 Subject: [PATCH 14/18] frontend: fix obi_demux and addr decode --- src/frontend/inst64/idma_inst64_top.sv | 62 +++++++++++++------------- 1 file changed, 32 insertions(+), 30 deletions(-) diff --git a/src/frontend/inst64/idma_inst64_top.sv b/src/frontend/inst64/idma_inst64_top.sv index 02d5c516..1d130620 100644 --- a/src/frontend/inst64/idma_inst64_top.sv +++ b/src/frontend/inst64/idma_inst64_top.sv @@ -73,7 +73,7 @@ module idma_inst64_top #( localparam int unsigned RepWidth = 32'd32; localparam int unsigned NumDim = 32'd2; localparam int unsigned BufferDepth = 32'd64; - localparam int unsigned NumRules = 32'd4; + localparam int unsigned NumRules = 32'd5; // derived constants and types localparam int unsigned StrbWidth = AxiDataWidth / 32'd8; @@ -149,6 +149,7 @@ module idma_inst64_top #( obi_req_t [NumChannels-1:0] obi_read_req, obi_write_req; obi_res_t [NumChannels-1:0] obi_read_rsp, obi_write_rsp; logic [NumChannels-1:0] obi_we_q, obi_we_d; + logic obi_req_o_rready; // backend signals idma_req_t [NumChannels-1:0] idma_req; @@ -194,12 +195,12 @@ module idma_inst64_top #( logic acc_res_ready; // decoder signals - logic [NumRules-1:0] idx_src; - logic idx_src_valid; - logic idx_src_error; - logic [NumRules-1:0] idx_dst; - logic idx_dst_valid; - logic idx_dst_error; + logic [$clog2(NumRules)-1:0] idx_src; + logic idx_src_valid; + logic idx_src_error; + logic [$clog2(NumRules)-1:0] idx_dst; + logic idx_dst_valid; + logic idx_dst_error; //-------------------------------------- // Backend instantiation @@ -310,13 +311,14 @@ module idma_inst64_top #( stream_demux #( .N_OUP ( 32'd2 ) - ) i_stream_demux ( + ) i_obi_rw_demux ( .inp_valid_i ( obi_res_i[c].rvalid ), - .inp_ready_o ( obi_req_o[c].rready ), - .oup_sel_i ( obi_we_q[c] ), + .inp_ready_o ( obi_req_o_rready ), + .oup_sel_i ( obi_we_d[c] ), .oup_valid_o ( {obi_write_rsp[c].rvalid , obi_read_rsp[c].rvalid } ), .oup_ready_i ( {obi_write_req[c].rready , obi_read_req[c].rready } ) ); + assign obi_req_o[c].rready = obi_req_o_rready; assign busy_o[c] = (|idma_busy[c]) | idma_nd_busy[c]; @@ -433,33 +435,33 @@ module idma_inst64_top #( // Address Decode addr_decode #( - .NoIndices ( 32'd2 ), - .NoRules ( 32'd2 ), - .addr_t ( addr_t ), - .rule_t ( addr_rule_t ) + .NoIndices ( $clog2(NumRules) ), + .NoRules ( NumRules ), + .addr_t ( addr_t ), + .rule_t ( addr_rule_t ) ) i_idma_src_decode ( .addr_i ( idma_fe_req_d.burst_req.src_addr[AxiAddrWidth-1:0] ), - .addr_map_i ( addr_map_i ), - .idx_o ( idx_src ), - .dec_valid_o ( idx_src_valid ), - .dec_error_o ( idx_src_error ), - .en_default_idx_i ( 1'b1 ), - .default_idx_i ( 32'd4 ) + .addr_map_i ( addr_map_i ), + .idx_o ( idx_src ), + .dec_valid_o ( idx_src_valid ), + .dec_error_o ( idx_src_error ), + .en_default_idx_i ( 1'b1 ), + .default_idx_i ( 32'd4 ) ); // address decoder for destination address addr_decode #( - .NoIndices ( 32'd2 ), - .addr_t ( addr_t ), - .NoRules ( 32'd2 ), - .rule_t ( addr_rule_t ) + .NoIndices ( $clog2(NumRules) ), + .addr_t ( addr_t ), + .NoRules ( NumRules ), + .rule_t ( addr_rule_t ) ) i_idma_dst_decode ( .addr_i ( idma_fe_req_d.burst_req.dst_addr[AxiAddrWidth-1:0] ), - .addr_map_i ( addr_map_i ), - .idx_o ( idx_dst ), - .dec_valid_o ( idx_dst_valid ), - .dec_error_o ( idx_dst_error ), - .en_default_idx_i ( 1'b1 ), - .default_idx_i ( 32'd4 ) + .addr_map_i ( addr_map_i ), + .idx_o ( idx_dst ), + .dec_valid_o ( idx_dst_valid ), + .dec_error_o ( idx_dst_error ), + .en_default_idx_i ( 1'b1 ), + .default_idx_i ( 32'd4 ) ); From b7e5cbb7b49605fdd10ffc1ed300855e1d1e363f Mon Sep 17 00:00:00 2001 From: Lucia Luzi Date: Wed, 12 Feb 2025 11:24:47 +0100 Subject: [PATCH 15/18] frontend: fix obi req valid signal & typos --- src/frontend/inst64/idma_inst64_top.sv | 82 +++++++++++++++----------- src/idma_pkg.sv | 5 ++ 2 files changed, 51 insertions(+), 36 deletions(-) diff --git a/src/frontend/inst64/idma_inst64_top.sv b/src/frontend/inst64/idma_inst64_top.sv index 1d130620..c9c84cbf 100644 --- a/src/frontend/inst64/idma_inst64_top.sv +++ b/src/frontend/inst64/idma_inst64_top.sv @@ -19,6 +19,7 @@ module idma_inst64_top #( parameter int unsigned NumAxInFlight = 32'd3, parameter int unsigned DMAReqFifoDepth = 32'd3, parameter int unsigned NumChannels = 32'd1, + parameter bit TCDMAliasEnable = 1'b0, parameter int unsigned DMATracing = 32'd0, parameter type axi_ar_chan_t = logic, parameter type axi_aw_chan_t = logic, @@ -43,9 +44,6 @@ module idma_inst64_top #( // AXI4 bus output axi_req_t [NumChannels-1:0] axi_req_o, input axi_res_t [NumChannels-1:0] axi_res_i, - // Memory Init - output init_req_t [NumChannels-1:0] init_req_o, - input init_rsp_t [NumChannels-1:0] init_res_i, // OBI interconnect output obi_req_t [NumChannels-1:0] obi_req_o, input obi_res_t [NumChannels-1:0] obi_res_i, @@ -64,7 +62,7 @@ module idma_inst64_top #( // performance output output dma_events_t [NumChannels-1:0] events_o, // address decode map - input addr_rule_t [3:0] addr_map_i + input addr_rule_t [TCDMAliasEnable:0] addr_map_i ); // constants @@ -143,7 +141,8 @@ module idma_inst64_top #( // internal Init channels init_req_t [NumChannels-1:0] init_read_req, init_write_req; init_rsp_t [NumChannels-1:0] init_read_rsp, init_write_rsp; - logic [7:0] init_read_rsp_byte; + logic [NumChannels-1:0][7:0] init_read_req_byte; + logic [NumChannels-1:0][7:0] init_read_rsq_byte; // internal OBI channels obi_req_t [NumChannels-1:0] obi_read_req, obi_write_req; @@ -195,10 +194,12 @@ module idma_inst64_top #( logic acc_res_ready; // decoder signals - logic [$clog2(NumRules)-1:0] idx_src; + localparam int unsigned NoRules = (1 + TCDMAliasEnable); + localparam int unsigned NoIndices = 1; + logic [NoIndices-1:0] idx_src; logic idx_src_valid; logic idx_src_error; - logic [$clog2(NumRules)-1:0] idx_dst; + logic [NoIndices-1:0] idx_dst; logic idx_dst_valid; logic idx_dst_error; @@ -216,7 +217,7 @@ module idma_inst64_top #( .TFLenWidth ( TFLenWidth ), .MemSysDepth ( 32'd16 ), .CombinedShifter ( 1'b1 ), - .RAWCouplingAvail ( 1'b1 ), + .RAWCouplingAvail ( 1'b0 ), .MaskInvalidData ( 1'b0 ), .HardwareLegalizer ( 1'b1 ), .RejectZeroTransfers ( 1'b1 ), @@ -278,7 +279,7 @@ module idma_inst64_top #( // INIT setup spill_register #( - .T ( init_req_t ) + .T ( logic [7:0] ) ) i_spill_register_init ( .clk_i, .rst_ni, @@ -287,25 +288,25 @@ module idma_inst64_top #( .data_i ( init_read_req[c].req_chan.cfg[7:0] ), .valid_o ( init_read_rsp[c].rsp_valid ), .ready_i ( init_read_req[c].rsp_ready ), - .data_o ( init_read_rsp_byte ) + .data_o ( init_read_req_byte[c] ) ); - assign init_read_rsp[c].rsp_chan.init = {{StrbWidth}{init_read_rsp_byte}}; + assign init_read_rsp[c].rsp_chan.init = {{StrbWidth}{init_read_req_byte[c]}}; - // OBI mux read or write - assign obi_we_d[c] = obi_write_req[c].a.we; + // prefer read request if both were valid (but shouldn't happen) + assign obi_we_d[c] = (~obi_read_req[c].req & obi_write_req[c].req); + `FF(obi_we_q[c], obi_we_d[c], '0, clk_i, rst_ni) - stream_mux #( - .DATA_T ( obi_req_t ), + .DATA_T ( obi_a_chan_t ), .N_INP ( 32'd2 ) ) i_obi_rw_mux ( - .inp_data_i ( {obi_write_req[c], obi_read_req[c] } ), - .inp_valid_i ( {(obi_write_req[c] != '0), (obi_read_req[c] != '0)} ), + .inp_data_i ( {obi_write_req[c].a, obi_read_req[c].a } ), + .inp_valid_i ( {obi_write_req[c].req, obi_read_req[c].req } ), .inp_ready_o ( {obi_write_rsp[c].gnt, obi_read_rsp[c].gnt } ), .inp_sel_i ( obi_we_d[c] ), - .oup_data_o ( obi_req_o[c] ), - .oup_valid_o ( ), + .oup_data_o ( obi_req_o[c].a ), + .oup_valid_o ( obi_req_o[c].req ), .oup_ready_i ( obi_res_i[c].gnt ) ); @@ -313,13 +314,19 @@ module idma_inst64_top #( .N_OUP ( 32'd2 ) ) i_obi_rw_demux ( .inp_valid_i ( obi_res_i[c].rvalid ), - .inp_ready_o ( obi_req_o_rready ), - .oup_sel_i ( obi_we_d[c] ), + .inp_ready_o ( /*obi_req_o_rready*/ ), + .oup_sel_i ( obi_we_q[c] ), .oup_valid_o ( {obi_write_rsp[c].rvalid , obi_read_rsp[c].rvalid } ), .oup_ready_i ( {obi_write_req[c].rready , obi_read_req[c].rready } ) ); - assign obi_req_o[c].rready = obi_req_o_rready; + always_comb begin : gen_obi_response + if (obi_we_q[c]) begin + assign obi_write_rsp[c].r = obi_res_i[c].r; + end else begin + assign obi_read_rsp[c].r = obi_res_i[c].r; + end + end assign busy_o[c] = (|idma_busy[c]) | idma_nd_busy[c]; end @@ -435,8 +442,8 @@ module idma_inst64_top #( // Address Decode addr_decode #( - .NoIndices ( $clog2(NumRules) ), - .NoRules ( NumRules ), + .NoIndices ( NoIndices ), + .NoRules ( NoRules ), .addr_t ( addr_t ), .rule_t ( addr_rule_t ) ) i_idma_src_decode ( @@ -446,13 +453,13 @@ module idma_inst64_top #( .dec_valid_o ( idx_src_valid ), .dec_error_o ( idx_src_error ), .en_default_idx_i ( 1'b1 ), - .default_idx_i ( 32'd4 ) + .default_idx_i ( idma_pkg::ToSoC ) ); // address decoder for destination address addr_decode #( - .NoIndices ( $clog2(NumRules) ), + .NoIndices ( NoIndices ), .addr_t ( addr_t ), - .NoRules ( NumRules ), + .NoRules ( NoRules ), .rule_t ( addr_rule_t ) ) i_idma_dst_decode ( .addr_i ( idma_fe_req_d.burst_req.dst_addr[AxiAddrWidth-1:0] ), @@ -461,7 +468,7 @@ module idma_inst64_top #( .dec_valid_o ( idx_dst_valid ), .dec_error_o ( idx_dst_error ), .en_default_idx_i ( 1'b1 ), - .default_idx_i ( 32'd4 ) + .default_idx_i ( idma_pkg::ToSoC ) ); @@ -692,25 +699,28 @@ module idma_inst64_top #( if (idma_fe_req_d.burst_req.opt.src_protocol != idma_pkg::INIT) begin - assign idx_src = (idx_src_error) ? 32'd4 : (idx_src); - assign idx_dst = (idx_dst_error) ? 32'd4 : (idx_dst); + // error handling + // assign idx_src = (idx_src_error) ? 32'd4 : (idx_src); + // assign idx_dst = (idx_dst_error) ? 32'd4 : (idx_dst); unique casez (idx_src) - 32'd0, 32'd2: begin //TCDM - idma_fe_req_d.burst_req.opt.src_protocol = idma_pkg::OBI; + idma_pkg::ToSoC : begin //SoCDMAOut + idma_fe_req_d.burst_req.opt.src_protocol = idma_pkg::AXI; end - 32'd1, 32'd3 : begin //ZeroMem + idma_pkg::TCDMDMA : begin //TCDM + idma_fe_req_d.burst_req.opt.src_protocol = idma_pkg::OBI; end default : begin //SoCDMAOut idma_fe_req_d.burst_req.opt.src_protocol = idma_pkg::AXI; end endcase unique casez (idx_dst) - 32'd0, 32'd2: begin //TCDM - idma_fe_req_d.burst_req.opt.dst_protocol = idma_pkg::OBI; + idma_pkg::ToSoC : begin //SoCDMAOut + idma_fe_req_d.burst_req.opt.dst_protocol = idma_pkg::AXI; end - 32'd1, 32'd3 : begin //ZeroMem + idma_pkg::TCDMDMA : begin //TCDM + idma_fe_req_d.burst_req.opt.dst_protocol = idma_pkg::OBI; end default : begin //SoCDMAOut idma_fe_req_d.burst_req.opt.dst_protocol = idma_pkg::AXI; diff --git a/src/idma_pkg.sv b/src/idma_pkg.sv index 808319ac..a7886ad6 100644 --- a/src/idma_pkg.sv +++ b/src/idma_pkg.sv @@ -100,4 +100,9 @@ package idma_pkg; /// Supported Protocols type typedef logic[1:0] protocol_t; + typedef enum logic { + TCDMDMA = 0, + ToSoC = 1 + } dma_addr_map_e; + endpackage From e8d86ec0cfd2d48959a281c53e78fe19cc289b4f Mon Sep 17 00:00:00 2001 From: Lucia Luzi Date: Wed, 12 Feb 2025 16:06:24 +0100 Subject: [PATCH 16/18] frontend: remove assign statement --- src/frontend/inst64/idma_inst64_top.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/frontend/inst64/idma_inst64_top.sv b/src/frontend/inst64/idma_inst64_top.sv index c9c84cbf..44066133 100644 --- a/src/frontend/inst64/idma_inst64_top.sv +++ b/src/frontend/inst64/idma_inst64_top.sv @@ -322,9 +322,9 @@ module idma_inst64_top #( always_comb begin : gen_obi_response if (obi_we_q[c]) begin - assign obi_write_rsp[c].r = obi_res_i[c].r; + obi_write_rsp[c].r = obi_res_i[c].r; end else begin - assign obi_read_rsp[c].r = obi_res_i[c].r; + obi_read_rsp[c].r = obi_res_i[c].r; end end From 7a95909f6dfb1b8d3aaeed12782748325fb751ee Mon Sep 17 00:00:00 2001 From: Lucia Luzi Date: Tue, 4 Mar 2025 18:41:18 +0100 Subject: [PATCH 17/18] frontend: fix DMINIT: rm src protocol --- src/frontend/inst64/idma_inst64_top.sv | 46 ++++++++++---------------- 1 file changed, 17 insertions(+), 29 deletions(-) diff --git a/src/frontend/inst64/idma_inst64_top.sv b/src/frontend/inst64/idma_inst64_top.sv index 44066133..a0032e5c 100644 --- a/src/frontend/inst64/idma_inst64_top.sv +++ b/src/frontend/inst64/idma_inst64_top.sv @@ -70,7 +70,7 @@ module idma_inst64_top #( localparam int unsigned TFLenWidth = AxiAddrWidth; localparam int unsigned RepWidth = 32'd32; localparam int unsigned NumDim = 32'd2; - localparam int unsigned BufferDepth = 32'd64; + localparam int unsigned BufferDepth = 32'd16; localparam int unsigned NumRules = 32'd5; // derived constants and types @@ -314,7 +314,7 @@ module idma_inst64_top #( .N_OUP ( 32'd2 ) ) i_obi_rw_demux ( .inp_valid_i ( obi_res_i[c].rvalid ), - .inp_ready_o ( /*obi_req_o_rready*/ ), + .inp_ready_o ( obi_req_o[c].rready ), .oup_sel_i ( obi_we_q[c] ), .oup_valid_o ( {obi_write_rsp[c].rvalid , obi_read_rsp[c].rvalid } ), .oup_ready_i ( {obi_write_req[c].rready , obi_read_req[c].rready } ) @@ -587,21 +587,16 @@ module idma_inst64_top #( // use init for memset idma_inst64_snitch_pkg::DMINIT : begin - // Parse the transfer parameters from the register or immediate. - unique casez (acc_req_i.data_op) - idma_inst64_snitch_pkg::DMINIT : begin - idma_fe_init_cfg = acc_req_i.data_op[21:20]; - idma_fe_sel_chan = acc_req_i.data_op[24:22]; - end - default:; - endcase + // Parse the transfer parameters from the immediate. + idma_fe_init_cfg = acc_req_i.data_op[21:20]; + idma_fe_sel_chan = acc_req_i.data_op[24:22]; + dma_op_name = "DMINIT"; is_dma_op = 1'b1; idma_fe_req_d.burst_req.opt.axi_id = idma_fe_sel_chan; idma_fe_req_d.burst_req.length = acc_req_i.data_arga; idma_fe_req_d.burst_req.opt.src_protocol = idma_pkg::INIT; - idma_fe_req_d.burst_req.opt.dst_protocol = idma_pkg::INIT; // save correct value as src addr, depending on cfg case (idma_fe_init_cfg) @@ -610,12 +605,6 @@ module idma_inst64_top #( // else: DMSRC already added the value to idma_fe_req_d.burst_req.src_addr[AxiAddrWidth-1:0] endcase - // set strides and reps - // 1 byte value is repeated 'size' times - idma_fe_req_d.d_req[0].src_strides = 0; - idma_fe_req_d.d_req[0].dst_strides = 1'b1; - idma_fe_req_d.d_req[0].reps = acc_req_i.data_arga; - // Perform the following sequence: // 1. wait for acc response channel to be ready (pready) // 2. request twod transfer (valid) @@ -715,19 +704,18 @@ module idma_inst64_top #( idma_fe_req_d.burst_req.opt.src_protocol = idma_pkg::AXI; end endcase - unique casez (idx_dst) - idma_pkg::ToSoC : begin //SoCDMAOut - idma_fe_req_d.burst_req.opt.dst_protocol = idma_pkg::AXI; - end - idma_pkg::TCDMDMA : begin //TCDM - idma_fe_req_d.burst_req.opt.dst_protocol = idma_pkg::OBI; - end - default : begin //SoCDMAOut - idma_fe_req_d.burst_req.opt.dst_protocol = idma_pkg::AXI; - end - endcase end - + unique casez (idx_dst) + idma_pkg::ToSoC : begin //SoCDMAOut + idma_fe_req_d.burst_req.opt.dst_protocol = idma_pkg::AXI; + end + idma_pkg::TCDMDMA : begin //TCDM + idma_fe_req_d.burst_req.opt.dst_protocol = idma_pkg::OBI; + end + default : begin //SoCDMAOut + idma_fe_req_d.burst_req.opt.dst_protocol = idma_pkg::AXI; + end + endcase end // twod handling From d7ad14b31e82e50c2973a70400ccc460f3f617f4 Mon Sep 17 00:00:00 2001 From: Lucia Luzi Date: Tue, 4 Mar 2025 18:42:16 +0100 Subject: [PATCH 18/18] backend: default rsp to zero in obi write --- src/backend/idma_obi_write.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/backend/idma_obi_write.sv b/src/backend/idma_obi_write.sv index d79163c1..5ad370c0 100644 --- a/src/backend/idma_obi_write.sv +++ b/src/backend/idma_obi_write.sv @@ -157,7 +157,8 @@ module idma_obi_write #( // Write response //-------------------------------------- // connect w_dp response payload - assign w_dp_rsp_o = '0; + assign w_dp_rsp_o.resp = '0; + assign w_dp_rsp_o.user = '0; // w_dp_valid_o is triggered once the write answer is here assign w_dp_valid_o = write_rsp_i.rvalid;