Merge pull request #338 from rmsyn/riscv/register/mseccfg

riscv: add mseccfg/h CSR registers

Author: romancardenas

riscv/CHANGELOG.md

@@ -19,6 +19,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - New `riscv::register::xip::clear_pending` atomic function for `mip` and `sip` registers.
   This function is marked as `unsafe`, as its availability depends both on the target chip
   and the target interrupt source.
+- Add `mseccfg` CSR
+- Add `mseccfgh` CSR
 
 ### Changed
 

riscv/src/register.rs

@@ -113,6 +113,9 @@ pub use self::mhpmeventx::*;
 
 // Machine configuration
 pub mod mconfigptr;
+pub mod mseccfg;
+#[cfg(any(test, target_arch = "riscv32"))]
+pub mod mseccfgh;
 
 #[cfg(test)]
 mod tests;

riscv/src/register/mip.rs

@@ -84,15 +84,11 @@ mod tests {
 
     #[test]
     fn test_mip() {
-        let mut m = Mip::from_bits(0);
+        let mip = Mip::from_bits(0);
 
-        test_csr_field!(m, ssoft);
-        test_csr_field!(m, stimer);
-        test_csr_field!(m, sext);
-
-        assert!(!m.msoft());
-        assert!(!m.mtimer());
-        assert!(!m.mext());
+        assert!(!mip.msoft());
+        assert!(!mip.mtimer());
+        assert!(!mip.mext());
 
         assert!(Mip::from_bits(1 << 3).msoft());
         assert!(Mip::from_bits(1 << 7).mtimer());

riscv/src/register/mseccfg.rs

@@ -0,0 +1,118 @@
+//! mseccfg register
+
+#[cfg(not(target_arch = "riscv32"))]
+const MASK: usize = 0x3_0000_0707;
+#[cfg(target_arch = "riscv32")]
+const MASK: usize = 0x707;
+
+read_write_csr! {
+    /// mseccfg register
+    Mseccfg: 0x747,
+    mask: MASK,
+}
+
+read_write_csr_field! {
+    Mseccfg,
+    /// Machine-Mode Lockdown
+    ///
+    /// # Note
+    ///
+    /// Defined in in the [Smepmp](https://raw.githubusercontent.com/riscv/riscv-tee/main/Smepmp/Smepmp.pdf) extension.
+    mml: 0,
+}
+
+read_write_csr_field! {
+    Mseccfg,
+    /// Machine-Mode Whitelist Policy
+    ///
+    /// # Note
+    ///
+    /// Defined in in the [Smepmp](https://raw.githubusercontent.com/riscv/riscv-tee/main/Smepmp/Smepmp.pdf) extension.
+    mmwp: 1,
+}
+
+read_write_csr_field! {
+    Mseccfg,
+    /// Rule Locking Bypass
+    ///
+    /// # Note
+    ///
+    /// Defined in in the [Smepmp](https://raw.githubusercontent.com/riscv/riscv-tee/main/Smepmp/Smepmp.pdf) extension.
+    rlb: 2,
+}
+
+read_write_csr_field! {
+    Mseccfg,
+    /// User-mode seed
+    ///
+    /// # Note
+    ///
+    /// Defined in in the [Zkr](https://github.com/riscv/riscv-crypto/releases/download/v1.0.1-scalar/riscv-crypto-spec-scalar-v1.0.1.pdf) extension.
+    useed: 8,
+}
+
+read_write_csr_field! {
+    Mseccfg,
+    /// Supervisor-mode seed
+    ///
+    /// # Note
+    ///
+    /// Defined in in the [Zkr](https://github.com/riscv/riscv-crypto/releases/download/v1.0.1-scalar/riscv-crypto-spec-scalar-v1.0.1.pdf) extension.
+    sseed: 9,
+}
+
+read_write_csr_field! {
+    Mseccfg,
+    /// Machine-mode Landing Pad Enable
+    ///
+    /// # Note
+    ///
+    /// Defined in in the [Zicfilp](https://github.com/riscv/riscv-cfi/releases/download/v1.0/riscv-cfi.pdf) extension.
+    mlpe: 10,
+}
+
+csr_field_enum! {
+    /// Pointer Masking Machine-mode
+    PMM {
+        default: Disabled,
+        Disabled = 0,
+        EnabledXlen57 = 2,
+        EnabledXlen48 = 3,
+    }
+}
+
+#[cfg(not(target_arch = "riscv32"))]
+read_write_csr_field! {
+    Mseccfg,
+    /// Pointer Masking Machine-mode
+    ///
+    /// # Note
+    ///
+    /// Defined in in the [Smmpm](https://github.com/riscv/riscv-j-extension/releases/download/pointer-masking-ratified/pointer-masking-ratified.pdf) extension.
+    pmm,
+    PMM: [32:33],
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_mseccfg() {
+        let mut mseccfg = Mseccfg::from_bits(0);
+
+        test_csr_field!(mseccfg, mml);
+        test_csr_field!(mseccfg, mmwp);
+        test_csr_field!(mseccfg, rlb);
+        test_csr_field!(mseccfg, useed);
+        test_csr_field!(mseccfg, sseed);
+        test_csr_field!(mseccfg, mlpe);
+
+        #[cfg(not(target_arch = "riscv32"))]
+        {
+            test_csr_field!(mseccfg, pmm: PMM::Disabled);
+            test_csr_field!(mseccfg, pmm: PMM::EnabledXlen57);
+            test_csr_field!(mseccfg, pmm: PMM::EnabledXlen48);
+        }
+    }
+}

riscv/src/register/mseccfgh.rs

@@ -0,0 +1,34 @@
+//! mseccfgh register
+
+use super::mseccfg::PMM;
+
+read_write_csr! {
+    /// mseccfgh register
+    Mseccfgh: 0x757,
+    mask: 0x3,
+}
+
+read_write_csr_field! {
+    Mseccfgh,
+    /// Pointer Masking Machine-mode
+    ///
+    /// # Note
+    ///
+    /// Defined in in the [Smmpm](https://github.com/riscv/riscv-j-extension/releases/download/pointer-masking-ratified/pointer-masking-ratified.pdf) extension.
+    pmm,
+    PMM: [0:1],
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_mseccfgh() {
+        let mut mseccfgh = Mseccfgh::from_bits(0);
+
+        test_csr_field!(mseccfgh, pmm: PMM::Disabled);
+        test_csr_field!(mseccfgh, pmm: PMM::EnabledXlen57);
+        test_csr_field!(mseccfgh, pmm: PMM::EnabledXlen48);
+    }
+}

riscv/src/register/sip.rs

@@ -60,9 +60,8 @@ mod tests {
 
     #[test]
     fn test_sip() {
-        let mut sip = Sip::from_bits(0);
+        let sip = Sip::from_bits(0);
 
-        test_csr_field!(sip, ssoft);
         assert!(!sip.stimer());
         assert!(!sip.sext());
 

typos.toml

@@ -1,2 +1,2 @@
 [default]
-extend-ignore-re = ["[Ss][Ii][Ee]", "[Ss][Xx][Ll]"]
+extend-ignore-re = ["[Ss][Ii][Ee]", "[Ss][Xx][Ll]", "[.]?useed[.,:]?"]