Merge pull request #334 from jsgf/fix-mcause-interrupt

Allow 64-bit Mcause::from_bits on rv64

Author: romancardenas

riscv/CHANGELOG.md

@@ -19,6 +19,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Use `cfg(any(target_arch = "riscv32", target_arch = "riscv64"))` instead of `cfg(riscv)`.
 - `riscv::pac_enum(unsafe CoreInterrupt)` now locates the vector table at the `.trap.vector`
   section instead of `.trap`.
+- Allow all bits to be set in Mcause::from_bits on 64-bit targets.
 
 ### Removed
 

riscv/src/register/mcause.rs

@@ -5,7 +5,7 @@ pub use crate::interrupt::Trap;
 read_only_csr! {
     /// `mcause` register
     Mcause: 0x342,
-    mask: 0xffff_ffff,
+    mask: usize::MAX,
 }
 
 #[cfg(target_arch = "riscv32")]