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clippy
1 parent 63aeaf6 commit 67ee9d8

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5 files changed

+4
-7
lines changed

5 files changed

+4
-7
lines changed

src/flash.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ pub struct FlashWriter<'a> {
6363
flash_sz: FlashSize,
6464
verify: bool,
6565
}
66-
impl<'a> FlashWriter<'a> {
66+
impl FlashWriter<'_> {
6767
fn unlock(&mut self) -> Result<()> {
6868
// Wait for any ongoing operations
6969
while self.flash.sr.sr().read().bsy().bit_is_set() {}
@@ -245,7 +245,7 @@ impl<'a> FlashWriter<'a> {
245245

246246
// Flash is written 16 bits at a time, so combine two bytes to get a
247247
// half-word
248-
let hword: u16 = (data[idx] as u16) | (data[idx + 1] as u16) << 8;
248+
let hword: u16 = (data[idx] as u16) | ((data[idx + 1] as u16) << 8);
249249

250250
// NOTE(unsafe) Write to FLASH area with no side effects
251251
unsafe { core::ptr::write_volatile(write_address, hword) };

src/gpio.rs

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -519,7 +519,6 @@ impl<const P: char, const N: u8, MODE> Pin<P, N, MODE> {
519519
before changing its mode to an output to avoid
520520
a short spike of an incorrect value
521521
*/
522-
523522
#[inline(always)]
524523
fn _set_state(&mut self, state: PinState) {
525524
match state {

src/i2c.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -282,7 +282,7 @@ impl<I2C: Instance> I2c<I2C> {
282282
fn send_addr(&self, addr: u8, read: bool) {
283283
self.i2c
284284
.dr()
285-
.write(|w| w.dr().set(addr << 1 | (u8::from(read))));
285+
.write(|w| w.dr().set((addr << 1) | (u8::from(read))));
286286
}
287287

288288
/// Generate STOP condition

src/rcc.rs

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -187,7 +187,6 @@ impl CFGR {
187187
/// let mut rcc = dp.RCC.constrain();
188188
/// let clocks = rcc.cfgr.freeze(&mut flash.acr);
189189
/// ```
190-
191190
#[inline(always)]
192191
pub fn freeze(self, acr: &mut ACR) -> Clocks {
193192
let cfg = Config::from_cfgr(self);

src/rtc.rs

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,6 @@ pub enum RestoredOrNewRtc<CS> {
4141
[examples/rtc.rs]: https://github.com/stm32-rs/stm32f1xx-hal/blob/v0.7.0/examples/rtc.rs
4242
[examples/blinky_rtc.rs]: https://github.com/stm32-rs/stm32f1xx-hal/blob/v0.7.0/examples/blinky_rtc.rs
4343
*/
44-
4544
pub struct Rtc<CS = RtcClkLse> {
4645
regs: RTC,
4746
_clock_source: PhantomData<CS>,
@@ -360,7 +359,7 @@ impl<CS> Rtc<CS> {
360359
// Wait for the APB1 interface to be ready
361360
while !self.regs.crl().read().rsf().bit() {}
362361

363-
self.regs.cnth().read().bits() << 16 | self.regs.cntl().read().bits()
362+
(self.regs.cnth().read().bits() << 16) | self.regs.cntl().read().bits()
364363
}
365364

366365
/// Enables triggering the RTC interrupt every time the RTC counter is increased

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