diff --git a/CHANGELOG.md b/CHANGELOG.md index fe4ffa27..c63bf3b0 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -15,7 +15,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). Add `RInto` trait and `Rmp` peripheral wrapper, add `remap` for peripherals. [#514] [#520] Remove `RemapStruct`s. [#462] [#506] [#509] - Use independent `Spi` and `SpiSlave` structures instead of `OP` generic [#462] -- Take `&Clocks` instead of `Clocks` [#498] +- Include `Clocks` in `Rcc`. Take `&mut Rcc/RCC` where possible [#498] [#536] - Update to `stm32f1` v0.16.0 [#503] [#534] - `Spi` now takes `Option` for `SCK`, `MISO`, `MOSI` [#514], add `SPIx::NoSck`, etc. [#537] @@ -77,6 +77,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). [#526]: https://github.com/stm32-rs/stm32f1xx-hal/pull/526 [#528]: https://github.com/stm32-rs/stm32f1xx-hal/pull/528 [#534]: https://github.com/stm32-rs/stm32f1xx-hal/pull/534 +[#536]: https://github.com/stm32-rs/stm32f1xx-hal/pull/536 ## [v0.10.0] - 2022-12-12 diff --git a/examples/adc-dma-circ.rs b/examples/adc-dma-circ.rs index ec8c7c54..ae1ab1c2 100644 --- a/examples/adc-dma-circ.rs +++ b/examples/adc-dma-circ.rs @@ -9,29 +9,30 @@ use panic_halt as _; use cortex_m::{asm, singleton}; use cortex_m_rt::entry; -use stm32f1xx_hal::{adc, dma::Half, pac, prelude::*}; +use stm32f1xx_hal::{adc, dma::Half, pac, prelude::*, rcc}; #[entry] fn main() -> ! { // Acquire peripherals let p = pac::Peripherals::take().unwrap(); let mut flash = p.FLASH.constrain(); - let rcc = p.RCC.constrain(); // Configure ADC clocks // Default value is the slowest possible ADC clock: PCLK2 / 8. Meanwhile ADC // clock is configurable. So its frequency may be tweaked to meet certain // practical needs. User specified value is be approximated using supported // prescaler values 2/4/6/8. - let clocks = rcc.cfgr.adcclk(2.MHz()).freeze(&mut flash.acr); + let mut rcc = p + .RCC + .freeze(rcc::Config::hsi().adcclk(2.MHz()), &mut flash.acr); - let dma_ch1 = p.DMA1.split().1; + let dma_ch1 = p.DMA1.split(&mut rcc).1; // Setup ADC - let adc1 = adc::Adc::new(p.ADC1, &clocks); + let adc1 = adc::Adc::new(p.ADC1, &mut rcc); // Setup GPIOA - let mut gpioa = p.GPIOA.split(); + let mut gpioa = p.GPIOA.split(&mut rcc); // Configure pa0 as an analog input let adc_ch0 = gpioa.pa0.into_analog(&mut gpioa.crl); diff --git a/examples/adc-dma-rx.rs b/examples/adc-dma-rx.rs index 4aeb3e25..9be4924a 100644 --- a/examples/adc-dma-rx.rs +++ b/examples/adc-dma-rx.rs @@ -9,29 +9,30 @@ use panic_halt as _; use cortex_m::{asm, singleton}; use cortex_m_rt::entry; -use stm32f1xx_hal::{adc, pac, prelude::*}; +use stm32f1xx_hal::{adc, pac, prelude::*, rcc}; #[entry] fn main() -> ! { // Acquire peripherals let p = pac::Peripherals::take().unwrap(); let mut flash = p.FLASH.constrain(); - let rcc = p.RCC.constrain(); // Configure ADC clocks // Default value is the slowest possible ADC clock: PCLK2 / 8. Meanwhile ADC // clock is configurable. So its frequency may be tweaked to meet certain // practical needs. User specified value is be approximated using supported // prescaler values 2/4/6/8. - let clocks = rcc.cfgr.adcclk(2.MHz()).freeze(&mut flash.acr); + let mut rcc = p + .RCC + .freeze(rcc::Config::hsi().adcclk(2.MHz()), &mut flash.acr); - let dma_ch1 = p.DMA1.split().1; + let dma_ch1 = p.DMA1.split(&mut rcc).1; // Setup ADC - let adc1 = adc::Adc::new(p.ADC1, &clocks); + let adc1 = adc::Adc::new(p.ADC1, &mut rcc); // Setup GPIOA - let mut gpioa = p.GPIOA.split(); + let mut gpioa = p.GPIOA.split(&mut rcc); // Configure pa0 as an analog input let adc_ch0 = gpioa.pa0.into_analog(&mut gpioa.crl); diff --git a/examples/adc.rs b/examples/adc.rs index dab7ec32..7a43b235 100644 --- a/examples/adc.rs +++ b/examples/adc.rs @@ -5,7 +5,7 @@ use panic_semihosting as _; use cortex_m_rt::entry; -use stm32f1xx_hal::{adc, pac, prelude::*}; +use stm32f1xx_hal::{adc, pac, prelude::*, rcc}; use cortex_m_semihosting::hprintln; @@ -14,24 +14,26 @@ fn main() -> ! { // Acquire peripherals let p = pac::Peripherals::take().unwrap(); let mut flash = p.FLASH.constrain(); - let rcc = p.RCC.constrain(); // Configure ADC clocks // Default value is the slowest possible ADC clock: PCLK2 / 8. Meanwhile ADC // clock is configurable. So its frequency may be tweaked to meet certain // practical needs. User specified value is be approximated using supported // prescaler values 2/4/6/8. - let clocks = rcc.cfgr.adcclk(2.MHz()).freeze(&mut flash.acr); - hprintln!("adc freq: {}", clocks.adcclk()); + let mut rcc = p + .RCC + .freeze(rcc::Config::hsi().adcclk(2.MHz()), &mut flash.acr); + + hprintln!("adc freq: {}", rcc.clocks.adcclk()); // Setup ADC - let mut adc1 = adc::Adc::new(p.ADC1, &clocks); + let mut adc1 = adc::Adc::new(p.ADC1, &mut rcc); #[cfg(any(feature = "stm32f103", feature = "connectivity"))] - let mut adc2 = adc::Adc::new(p.ADC2, &clocks); + let mut adc2 = adc::Adc::new(p.ADC2, &mut rcc); // Setup GPIOB - let mut gpiob = p.GPIOB.split(); + let mut gpiob = p.GPIOB.split(&mut rcc); // Configure pb0, pb1 as an analog input let mut ch0 = gpiob.pb0.into_analog(&mut gpiob.crl); diff --git a/examples/adc_temperature.rs b/examples/adc_temperature.rs index 19f62820..7465e409 100644 --- a/examples/adc_temperature.rs +++ b/examples/adc_temperature.rs @@ -5,7 +5,7 @@ use panic_semihosting as _; use cortex_m_rt::entry; -use stm32f1xx_hal::{pac, prelude::*}; +use stm32f1xx_hal::{pac, prelude::*, rcc}; use cortex_m_semihosting::hprintln; @@ -14,31 +14,34 @@ fn main() -> ! { // Acquire peripherals let p = pac::Peripherals::take().unwrap(); let mut flash = p.FLASH.constrain(); - let rcc = p.RCC.constrain(); - - let clocks = rcc - .cfgr - .use_hse(8.MHz()) - .sysclk(56.MHz()) - .pclk1(28.MHz()) - .adcclk(14.MHz()) - .freeze(&mut flash.acr); + let mut rcc = p.RCC.freeze( + rcc::Config::hse(8.MHz()) + .sysclk(56.MHz()) + .pclk1(28.MHz()) + .adcclk(14.MHz()), + &mut flash.acr, + ); + /* // Alternative configuration using dividers and multipliers directly - let clocks = rcc.cfgr.freeze_with_config(rcc::Config { - hse: Some(8_000_000), - pllmul: Some(7), - hpre: rcc::HPre::DIV1, - ppre1: rcc::PPre::DIV2, - ppre2: rcc::PPre::DIV1, - usbpre: rcc::UsbPre::DIV1_5, - adcpre: rcc::AdcPre::DIV2, - }, &mut flash.acr);*/ - hprintln!("sysclk freq: {}", clocks.sysclk()); - hprintln!("adc freq: {}", clocks.adcclk()); + let rcc = p.RCC.freeze_raw( + rcc::RawConfig { + hse: Some(8_000_000), + pllmul: Some(7), + hpre: rcc::HPre::Div1, + ppre1: rcc::PPre::Div2, + ppre2: rcc::PPre::Div1, + usbpre: rcc::UsbPre::Div1_5, + adcpre: rcc::AdcPre::Div2, + ..Default::default() + }, + &mut flash.acr, + );*/ + hprintln!("sysclk freq: {}", rcc.clocks.sysclk()); + hprintln!("adc freq: {}", rcc.clocks.adcclk()); // Setup ADC - let mut adc = p.ADC1.adc(&clocks); + let mut adc = p.ADC1.adc(&mut rcc); // Read temperature sensor loop { diff --git a/examples/blinky.rs b/examples/blinky.rs index fe6edf00..fd9adbf8 100644 --- a/examples/blinky.rs +++ b/examples/blinky.rs @@ -23,23 +23,16 @@ fn main() -> ! { // Get access to the device specific peripherals from the peripheral access crate let dp = pac::Peripherals::take().unwrap(); - // Take ownership over the raw flash and rcc devices and convert them into the corresponding - // HAL structs - let mut flash = dp.FLASH.constrain(); - let rcc = dp.RCC.constrain(); - - // Freeze the configuration of all the clocks in the system and store the frozen frequencies in - // `clocks` - let clocks = rcc.cfgr.freeze(&mut flash.acr); + let mut rcc = dp.RCC.constrain(); // Acquire the GPIOC peripheral - let mut gpioc = dp.GPIOC.split(); + let mut gpioc = dp.GPIOC.split(&mut rcc); // Configure gpio C pin 13 as a push-pull output. The `crh` register is passed to the function // in order to configure the port. For pins 0-7, crl should be passed instead. let mut led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh); // Configure the syst timer to trigger an update every second - let mut timer = Timer::syst(cp.SYST, &clocks).counter_hz(); + let mut timer = Timer::syst(cp.SYST, &rcc.clocks).counter_hz(); timer.start(1.Hz()).unwrap(); // Wait for the timer to trigger an update and change the state of the LED diff --git a/examples/blinky_generic.rs b/examples/blinky_generic.rs index 3d9efe65..e0110ce8 100644 --- a/examples/blinky_generic.rs +++ b/examples/blinky_generic.rs @@ -16,17 +16,14 @@ fn main() -> ! { let cp = cortex_m::Peripherals::take().unwrap(); let dp = pac::Peripherals::take().unwrap(); - let mut flash = dp.FLASH.constrain(); - let rcc = dp.RCC.constrain(); - - let clocks = rcc.cfgr.freeze(&mut flash.acr); + let mut rcc = dp.RCC.constrain(); // Acquire the GPIO peripherals - let mut gpioa = dp.GPIOA.split(); - let mut gpioc = dp.GPIOC.split(); + let mut gpioa = dp.GPIOA.split(&mut rcc); + let mut gpioc = dp.GPIOC.split(&mut rcc); // Configure the syst timer to trigger an update every second - let mut timer = Timer::syst(cp.SYST, &clocks).counter_hz(); + let mut timer = Timer::syst(cp.SYST, &rcc.clocks).counter_hz(); timer.start(1.Hz()).unwrap(); // Create an array of LEDS to blink diff --git a/examples/blinky_rtc.rs b/examples/blinky_rtc.rs index d53c44be..aff964da 100644 --- a/examples/blinky_rtc.rs +++ b/examples/blinky_rtc.rs @@ -22,17 +22,17 @@ fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); let mut pwr = dp.PWR; - let rcc = dp.RCC.constrain(); + let mut rcc = dp.RCC.constrain(); // Set up the GPIO pin - let mut gpioc = dp.GPIOC.split(); + let mut gpioc = dp.GPIOC.split(&mut rcc); let mut led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh); // Set up the RTC // Enable writes to the backup domain - let mut backup_domain = rcc.bkp.constrain(dp.BKP, &mut pwr); + let mut backup_domain = dp.BKP.constrain(&mut pwr, &mut rcc); // Start the RTC - let mut rtc = Rtc::new(dp.RTC, &mut backup_domain); + let mut rtc = Rtc::new(dp.RTC, &mut backup_domain, &mut rcc); let mut led_on = false; loop { diff --git a/examples/blinky_rtcalarm_irq.rs b/examples/blinky_rtcalarm_irq.rs index 23be255a..4ee704d0 100644 --- a/examples/blinky_rtcalarm_irq.rs +++ b/examples/blinky_rtcalarm_irq.rs @@ -78,10 +78,10 @@ fn main() -> ! { let dp = Peripherals::take().unwrap(); let mut pwr = dp.PWR; - let rcc = dp.RCC.constrain(); + let mut rcc = dp.RCC.constrain(); // Set up the GPIO pin - let mut gpioc = dp.GPIOC.split(); + let mut gpioc = dp.GPIOC.split(&mut rcc); let mut led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh); let _ = led.set_high(); // Turn off @@ -96,9 +96,9 @@ fn main() -> ! { // Set up the RTC // Enable writes to the backup domain - let mut backup_domain = rcc.bkp.constrain(dp.BKP, &mut pwr); + let mut backup_domain = dp.BKP.constrain(&mut pwr, &mut rcc); // Start the RTC - let mut rtc = Rtc::new(dp.RTC, &mut backup_domain); + let mut rtc = Rtc::new(dp.RTC, &mut backup_domain, &mut rcc); rtc.set_time(0); rtc.set_alarm(TOGGLE_INTERVAL_SECONDS); rtc.listen_alarm(); diff --git a/examples/blinky_timer_irq.rs b/examples/blinky_timer_irq.rs index 8350f0da..0b3129f7 100644 --- a/examples/blinky_timer_irq.rs +++ b/examples/blinky_timer_irq.rs @@ -18,6 +18,7 @@ use crate::hal::{ gpio::{gpioc, Output, PinState, PushPull}, pac::{interrupt, Interrupt, Peripherals, TIM2}, prelude::*, + rcc, timer::{CounterMs, Event}, }; @@ -69,16 +70,14 @@ fn TIM2() { fn main() -> ! { let dp = Peripherals::take().unwrap(); - let rcc = dp.RCC.constrain(); let mut flash = dp.FLASH.constrain(); - let clocks = rcc - .cfgr - .sysclk(8.MHz()) - .pclk1(8.MHz()) - .freeze(&mut flash.acr); + let mut rcc = dp.RCC.freeze( + rcc::Config::hsi().sysclk(8.MHz()).pclk1(8.MHz()), + &mut flash.acr, + ); // Configure PC13 pin to blink LED - let mut gpioc = dp.GPIOC.split(); + let mut gpioc = dp.GPIOC.split(&mut rcc); let led = Output::new(gpioc.pc13, &mut gpioc.crh, PinState::High); //or //let led = gpioc.pc13.into_push_pull_output_with_state(&mut gpioc.crh, PinState::High); @@ -87,7 +86,7 @@ fn main() -> ! { cortex_m::interrupt::free(|cs| *G_LED.borrow(cs).borrow_mut() = Some(led)); // Set up a timer expiring after 1s - let mut timer = dp.TIM2.counter_ms(&clocks); + let mut timer = dp.TIM2.counter_ms(&mut rcc); timer.start(1.secs()).unwrap(); // Generate an interrupt when the timer expires diff --git a/examples/can-echo.rs b/examples/can-echo.rs index b4c187c0..725c3670 100644 --- a/examples/can-echo.rs +++ b/examples/can-echo.rs @@ -10,29 +10,28 @@ use panic_halt as _; use bxcan::filter::Mask32; use cortex_m_rt::entry; use nb::block; -use stm32f1xx_hal::{pac, prelude::*}; +use stm32f1xx_hal::{pac, prelude::*, rcc}; #[entry] fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); let mut flash = dp.FLASH.constrain(); - let rcc = dp.RCC.constrain(); // To meet CAN clock accuracy requirements an external crystal or ceramic // resonator must be used. The blue pill has a 8MHz external crystal. // Other boards might have a crystal with another frequency or none at all. - rcc.cfgr.use_hse(8.MHz()).freeze(&mut flash.acr); + let mut rcc = dp.RCC.freeze(rcc::Config::hse(8.MHz()), &mut flash.acr); let mut can1 = { - let gpioa = dp.GPIOA.split(); + let gpioa = dp.GPIOA.split(&mut rcc); let rx = gpioa.pa11; let tx = gpioa.pa12; #[cfg(not(feature = "connectivity"))] - let can = dp.CAN.can(dp.USB, (tx, rx)); + let can = dp.CAN.can(dp.USB, (tx, rx), &mut rcc); #[cfg(feature = "connectivity")] - let can = dp.CAN1.can((tx, rx)); + let can = dp.CAN1.can((tx, rx), &mut rcc); // APB1 (PCLK1): 8MHz, Bit rate: 125kBit/s, Sample Point 87.5% // Value was calculated with http://www.bittiming.can-wiki.info/ @@ -47,8 +46,8 @@ fn main() -> ! { #[cfg(feature = "connectivity")] let _can2 = { - let gpiob = dp.GPIOB.split(); - let can = dp.CAN2.can((gpiob.pb6, gpiob.pb5)); + let gpiob = dp.GPIOB.split(&mut rcc); + let can = dp.CAN2.can((gpiob.pb6, gpiob.pb5), &mut rcc); // APB1 (PCLK1): 8MHz, Bit rate: 125kBit/s, Sample Point 87.5% // Value was calculated with http://www.bittiming.can-wiki.info/ diff --git a/examples/can-loopback.rs b/examples/can-loopback.rs index 81fac8c0..bed6a761 100644 --- a/examples/can-loopback.rs +++ b/examples/can-loopback.rs @@ -12,23 +12,22 @@ use panic_halt as _; use cortex_m_rt::entry; use nb::block; -use stm32f1xx_hal::{can::Can, gpio::Floating, pac, prelude::*}; +use stm32f1xx_hal::{can::Can, gpio::Floating, pac, prelude::*, rcc}; #[entry] fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); let mut flash = dp.FLASH.constrain(); - let rcc = dp.RCC.constrain(); // To meet CAN clock accuracy requirements, an external crystal or ceramic // resonator must be used. - rcc.cfgr.use_hse(8.MHz()).freeze(&mut flash.acr); + let mut rcc = dp.RCC.freeze(rcc::Config::hse(8.MHz()), &mut flash.acr); #[cfg(not(feature = "connectivity"))] - let can = Can::<_, Floating>::new_loopback(dp.CAN, dp.USB); + let can = Can::<_, Floating>::new_loopback(dp.CAN, dp.USB, &mut rcc); #[cfg(feature = "connectivity")] - let can = Can::<_, Floating>::new_loopback(dp.CAN1); + let can = Can::<_, Floating>::new_loopback(dp.CAN1, &mut rcc); // Use loopback mode: No pins need to be assigned to peripheral. // APB1 (PCLK1): 8MHz, Bit rate: 500Bit/s, Sample Point 87.5% @@ -109,7 +108,7 @@ fn main() -> ! { assert!(can.receive().is_err()); } - let mut gpiob = dp.GPIOB.split(); + let mut gpiob = dp.GPIOB.split(&mut rcc); let mut led = gpiob.pb9.into_push_pull_output(&mut gpiob.crh); led.set_high(); diff --git a/examples/can-rtic.rs b/examples/can-rtic.rs index aae46fa2..ba23760c 100644 --- a/examples/can-rtic.rs +++ b/examples/can-rtic.rs @@ -59,7 +59,7 @@ mod app { use stm32f1xx_hal::pac::CAN as CAN1; #[cfg(feature = "connectivity")] use stm32f1xx_hal::pac::CAN1; - use stm32f1xx_hal::{can::Can, prelude::*}; + use stm32f1xx_hal::{can::Can, prelude::*, rcc}; #[local] struct Local { @@ -75,27 +75,30 @@ mod app { #[init] fn init(cx: init::Context) -> (Shared, Local, init::Monotonics) { let mut flash = cx.device.FLASH.constrain(); - let rcc = cx.device.RCC.constrain(); - - let _clocks = rcc - .cfgr - .use_hse(8.MHz()) - .sysclk(64.MHz()) - .hclk(64.MHz()) - .pclk1(16.MHz()) - .pclk2(64.MHz()) - .freeze(&mut flash.acr); + let mut rcc = cx.device.RCC.freeze( + rcc::Config::hse(8.MHz()) + .sysclk(64.MHz()) + .hclk(64.MHz()) + .pclk1(16.MHz()) + .pclk2(64.MHz()), + &mut flash.acr, + ); // Select pins for CAN1. - let gpioa = cx.device.GPIOA.split(); + let gpioa = cx.device.GPIOA.split(&mut rcc); let can_rx_pin = gpioa.pa11; let can_tx_pin = gpioa.pa12; #[cfg(not(feature = "connectivity"))] - let can = Can::new(cx.device.CAN, cx.device.USB, (can_tx_pin, can_rx_pin)); + let can = Can::new( + cx.device.CAN, + cx.device.USB, + (can_tx_pin, can_rx_pin), + &mut rcc, + ); #[cfg(feature = "connectivity")] - let can = Can::new(cx.device.CAN1, (can_tx_pin, can_rx_pin)); + let can = Can::new(cx.device.CAN1, (can_tx_pin, can_rx_pin), &mut rcc); // APB1 (PCLK1): 16MHz, Bit rate: 1000kBit/s, Sample Point 87.5% // Value was calculated with http://www.bittiming.can-wiki.info/ diff --git a/examples/crc.rs b/examples/crc.rs index bf5829a9..c90ee504 100644 --- a/examples/crc.rs +++ b/examples/crc.rs @@ -15,7 +15,8 @@ use stm32f1xx_hal::{pac, prelude::*}; fn main() -> ! { let p = pac::Peripherals::take().unwrap(); - let mut crc = p.CRC.new(); + let mut rcc = p.RCC.constrain(); + let mut crc = p.CRC.new(&mut rcc); crc.reset(); crc.write(0x12345678); diff --git a/examples/delay-timer-blinky.rs b/examples/delay-timer-blinky.rs index 7cda54b3..6f12b43f 100644 --- a/examples/delay-timer-blinky.rs +++ b/examples/delay-timer-blinky.rs @@ -11,7 +11,7 @@ use panic_halt as _; // panic handler use cortex_m_rt::entry; use stm32f1xx_hal as hal; -use crate::hal::{pac, prelude::*}; +use crate::hal::{pac, prelude::*, rcc}; #[entry] fn main() -> ! { @@ -20,23 +20,19 @@ fn main() -> ! { cortex_m::peripheral::Peripherals::take(), ) { let mut flash = dp.FLASH.constrain(); + // Set up the system clock. We want to run at 48MHz for this one. + let mut rcc = dp + .RCC + .freeze(rcc::Config::hse(8.MHz()).sysclk(48.MHz()), &mut flash.acr); // Set up the LED. On the BluePill it's connected to pin PC13. - let mut gpioc = dp.GPIOC.split(); + let mut gpioc = dp.GPIOC.split(&mut rcc); let mut led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh); - // Set up the system clock. We want to run at 48MHz for this one. - let rcc = dp.RCC.constrain(); - let clocks = rcc - .cfgr - .use_hse(8.MHz()) - .sysclk(48.MHz()) - .freeze(&mut flash.acr); - // Create a delay abstraction based on general-pupose 32-bit timer TIM2 - //let mut delay = hal::timer::FTimerUs::new(dp.TIM2, &clocks).delay(); + //let mut delay = hal::timer::FTimerUs::new(dp.TIM2, &mut rcc).delay(); // or - let mut delay = dp.TIM2.delay_us(&clocks); + let mut delay = dp.TIM2.delay_us(&mut rcc); loop { // On for 1s, off for 3s. diff --git a/examples/delay.rs b/examples/delay.rs index ce83c661..8752cd3a 100644 --- a/examples/delay.rs +++ b/examples/delay.rs @@ -14,12 +14,9 @@ fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); let cp = cortex_m::Peripherals::take().unwrap(); - let mut flash = dp.FLASH.constrain(); - let rcc = dp.RCC.constrain(); + let mut rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.freeze(&mut flash.acr); - - let mut gpioc = dp.GPIOC.split(); + let mut gpioc = dp.GPIOC.split(&mut rcc); #[cfg(feature = "stm32f100")] let mut led = gpioc.pc9.into_push_pull_output(&mut gpioc.crh); @@ -30,9 +27,9 @@ fn main() -> ! { #[cfg(any(feature = "stm32f103", feature = "stm32f105", feature = "stm32f107"))] let mut led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh); - //let mut delay = hal::timer::Timer::syst(cp.SYST, &clocks).delay(); + //let mut delay = hal::timer::Timer::syst(cp.SYST, &rcc.clocks).delay(); // or - let mut delay = cp.SYST.delay(&clocks); + let mut delay = cp.SYST.delay(&rcc.clocks); loop { led.set_high(); diff --git a/examples/dynamic_gpio.rs b/examples/dynamic_gpio.rs index 6aa93fc5..ca4f7a5d 100644 --- a/examples/dynamic_gpio.rs +++ b/examples/dynamic_gpio.rs @@ -18,21 +18,14 @@ fn main() -> ! { // Get access to the device specific peripherals from the peripheral access crate let dp = pac::Peripherals::take().unwrap(); - // Take ownership over the raw flash and rcc devices and convert them into the corresponding - // HAL structs - let mut flash = dp.FLASH.constrain(); - let rcc = dp.RCC.constrain(); - - // Freeze the configuration of all the clocks in the system and store the frozen frequencies in - // `clocks` - let clocks = rcc.cfgr.freeze(&mut flash.acr); + let mut rcc = dp.RCC.constrain(); // Acquire the GPIOC peripheral - let mut gpioc = dp.GPIOC.split(); + let mut gpioc = dp.GPIOC.split(&mut rcc); let mut pin = gpioc.pc13.into_dynamic(&mut gpioc.crh); // Configure the syst timer to trigger an update every second - let mut timer = cp.SYST.counter_hz(&clocks); + let mut timer = cp.SYST.counter_hz(&rcc.clocks); timer.start(1.Hz()).unwrap(); // Wait for the timer to trigger an update and change the state of the LED diff --git a/examples/exti.rs b/examples/exti.rs index 57eb8c57..ceaa2fbc 100644 --- a/examples/exti.rs +++ b/examples/exti.rs @@ -42,12 +42,13 @@ fn main() -> ! { // initialization phase let mut p = pac::Peripherals::take().unwrap(); let _cp = cortex_m::peripheral::Peripherals::take().unwrap(); + let mut rcc = p.RCC.constrain(); { // the scope ensures that the int_pin reference is dropped before the first ISR can be executed. - let mut gpioa = p.GPIOA.split(); - let mut gpioc = p.GPIOC.split(); - let mut afio = p.AFIO.constrain(); + let mut gpioa = p.GPIOA.split(&mut rcc); + let mut gpioc = p.GPIOC.split(&mut rcc); + let mut afio = p.AFIO.constrain(&mut rcc); let led = unsafe { &mut *LED.as_mut_ptr() }; *led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh); diff --git a/examples/exti_rtic.rs b/examples/exti_rtic.rs index 07e449d9..23dfdce3 100644 --- a/examples/exti_rtic.rs +++ b/examples/exti_rtic.rs @@ -23,12 +23,13 @@ mod app { #[init] fn init(mut ctx: init::Context) -> (Shared, Local, init::Monotonics) { - let mut afio = ctx.device.AFIO.constrain(); + let mut rcc = ctx.device.RCC.constrain(); + let mut afio = ctx.device.AFIO.constrain(&mut rcc); - let mut gpioc = ctx.device.GPIOC.split(); + let mut gpioc = ctx.device.GPIOC.split(&mut rcc); let led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh); - let mut gpioa = ctx.device.GPIOA.split(); + let mut gpioa = ctx.device.GPIOA.split(&mut rcc); let mut button = gpioa.pa0.into_pull_down_input(&mut gpioa.crl); button.make_interrupt_source(&mut afio); button.enable_interrupt(&mut ctx.device.EXTI); diff --git a/examples/gpio_input.rs b/examples/gpio_input.rs index 5e5a6f81..f5f13788 100644 --- a/examples/gpio_input.rs +++ b/examples/gpio_input.rs @@ -24,15 +24,12 @@ fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); let cp = cortex_m::Peripherals::take().unwrap(); - let mut flash = dp.FLASH.constrain(); - let rcc = dp.RCC.constrain(); + let mut rcc = dp.RCC.constrain(); - let clock = rcc.cfgr.freeze(&mut flash.acr); - - let mut gpioa = dp.GPIOA.split(); - let mut _gpiob = dp.GPIOB.split(); - let mut gpioc = dp.GPIOC.split(); - let mut gpiod = dp.GPIOD.split(); + let mut gpioa = dp.GPIOA.split(&mut rcc); + let mut _gpiob = dp.GPIOB.split(&mut rcc); + let mut gpioc = dp.GPIOC.split(&mut rcc); + let mut gpiod = dp.GPIOD.split(&mut rcc); // red_led and green_led let mut red_led = gpioa @@ -42,7 +39,7 @@ fn main() -> ! { .pd2 .into_push_pull_output_with_state(&mut gpiod.crl, PinState::High); - let mut afio = dp.AFIO.constrain(); + let mut afio = dp.AFIO.constrain(&mut rcc); let (gpioa_pa15, _gpiob_pb3, _gpiob_pb4) = afio.mapr.disable_jtag(gpioa.pa15, _gpiob.pb3, _gpiob.pb4); @@ -53,7 +50,7 @@ fn main() -> ! { // The key_up for check buttons if long press. // if key_up is true, and buttons were not long press. let mut key_up: bool = true; - let mut delay = cp.SYST.delay(&clock); + let mut delay = cp.SYST.delay(&rcc.clocks); loop { let key_result = (key_0.is_low(), key_1.is_low()); if key_up && (key_result.0 || key_result.1) { diff --git a/examples/i2c-bme280/src/main.rs b/examples/i2c-bme280/src/main.rs index b341f042..8bb91a9f 100644 --- a/examples/i2c-bme280/src/main.rs +++ b/examples/i2c-bme280/src/main.rs @@ -27,6 +27,7 @@ use stm32f1xx_hal::{ i2c::{BlockingI2c, DutyCycle, Mode}, pac, prelude::*, + rcc, }; #[entry] @@ -39,25 +40,24 @@ fn main() -> ! { // Take ownership over the raw flash and rcc devices and convert them into the corresponding // HAL structs let mut flash = dp.FLASH.constrain(); - let rcc = dp.RCC.constrain(); - let mut afio = dp.AFIO.constrain(); - // Freeze the configuration of all the clocks in the system and store the frozen frequencies in - // `clocks` - let clocks = if 1 == 1 { - rcc.cfgr.use_hse(8.MHz()).freeze(&mut flash.acr) - } else { - // My blue pill with a stm32f103 clone dose not seem to respect rcc so will not compensate its pulse legths - // with a faster clock like this. And so the sensor dose not have time to respond to the START pulse. - // I would be interested if others with real stm32f103's can use this program with the faster clocks. - rcc.cfgr - .use_hse(8.MHz()) - .sysclk(48.MHz()) - .pclk1(6.MHz()) - .freeze(&mut flash.acr) - }; + let mut rcc = dp.RCC.freeze( + if 1 == 1 { + // Freeze the configuration of all the clocks in the system and store the frozen frequencies in + // `clocks` + rcc::Config::hse(8.MHz()) + } else { + // My blue pill with a stm32f103 clone dose not seem to respect rcc so will not compensate its pulse legths + // with a faster clock like this. And so the sensor dose not have time to respond to the START pulse. + // I would be interested if others with real stm32f103's can use this program with the faster clocks. + rcc::Config::hse(8.MHz()).sysclk(48.MHz()).pclk1(6.MHz()) + }, + &mut flash.acr, + ); + + let mut afio = dp.AFIO.constrain(&mut rcc); // Acquire the GPIOB peripheral - let mut gpiob = dp.GPIOB.split(); + let mut gpiob = dp.GPIOB.split(&mut rcc); let scl = gpiob.pb6; let sda = gpiob.pb7; diff --git a/examples/led.rs b/examples/led.rs index d5424197..ff51be56 100644 --- a/examples/led.rs +++ b/examples/led.rs @@ -23,7 +23,8 @@ use stm32f1xx_hal::{pac, prelude::*}; fn main() -> ! { let p = pac::Peripherals::take().unwrap(); - let mut gpioc = p.GPIOC.split(); + let mut rcc = p.RCC.constrain(); + let mut gpioc = p.GPIOC.split(&mut rcc); #[cfg(feature = "stm32f100")] gpioc.pc9.into_push_pull_output(&mut gpioc.crh).set_high(); diff --git a/examples/mfrc522.rs b/examples/mfrc522.rs index 04402445..771cb6e7 100644 --- a/examples/mfrc522.rs +++ b/examples/mfrc522.rs @@ -24,12 +24,9 @@ fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); let _stim = &mut cp.ITM.stim[0]; - let rcc = dp.RCC.constrain(); - let mut flash = dp.FLASH.constrain(); - let mut gpioa = dp.GPIOA.split(); - let mut gpioc = dp.GPIOC.split(); - - let clocks = rcc.cfgr.freeze(&mut flash.acr); + let mut rcc = dp.RCC.constrain(); + let mut gpioa = dp.GPIOA.split(&mut rcc); + let mut gpioc = dp.GPIOC.split(&mut rcc); let sck = gpioa.pa5; let miso = gpioa.pa6; @@ -39,7 +36,7 @@ fn main() -> ! { (Some(sck), Some(miso), Some(mosi)), MODE, 1.MHz(), - &clocks, + &mut rcc, ); let nss = gpioa.pa4.into_push_pull_output(&mut gpioa.crl); diff --git a/examples/mpu9250.rs b/examples/mpu9250.rs index 1ec945d1..183b21ea 100644 --- a/examples/mpu9250.rs +++ b/examples/mpu9250.rs @@ -19,13 +19,10 @@ fn main() -> ! { let cp = cortex_m::Peripherals::take().unwrap(); let dp = pac::Peripherals::take().unwrap(); - let mut flash = dp.FLASH.constrain(); - let rcc = dp.RCC.constrain(); + let mut rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.freeze(&mut flash.acr); - - let mut gpioa = dp.GPIOA.split(); - // let mut gpiob = dp.GPIOB.split(); + let mut gpioa = dp.GPIOA.split(&mut rcc); + // let mut gpiob = dp.GPIOB.split(&mut rcc); let nss = gpioa.pa4.into_push_pull_output(&mut gpioa.crl); @@ -44,10 +41,10 @@ fn main() -> ! { (Some(sck), Some(miso), Some(mosi)), mpu9250::MODE.into(), 1.MHz(), - &clocks, + &mut rcc, ); - let mut delay = cp.SYST.delay(&clocks); + let mut delay = cp.SYST.delay(&rcc.clocks); let mut mpu9250 = Mpu9250::marg_default(spi, nss, &mut delay).unwrap(); diff --git a/examples/multi_mode_gpio.rs b/examples/multi_mode_gpio.rs index c38ad244..e4c39400 100644 --- a/examples/multi_mode_gpio.rs +++ b/examples/multi_mode_gpio.rs @@ -17,21 +17,14 @@ fn main() -> ! { // Get access to the device specific peripherals from the peripheral access crate let dp = pac::Peripherals::take().unwrap(); - // Take ownership over the raw flash and rcc devices and convert them into the corresponding - // HAL structs - let mut flash = dp.FLASH.constrain(); - let rcc = dp.RCC.constrain(); - - // Freeze the configuration of all the clocks in the system and store the frozen frequencies in - // `clocks` - let clocks = rcc.cfgr.freeze(&mut flash.acr); + let mut rcc = dp.RCC.constrain(); // Acquire the GPIOC peripheral - let mut gpioc = dp.GPIOC.split(); + let mut gpioc = dp.GPIOC.split(&mut rcc); let mut pin = gpioc.pc13.into_floating_input(&mut gpioc.crh); // Configure the syst timer to trigger an update every second - let mut timer = Timer::syst(cp.SYST, &clocks).counter_hz(); + let mut timer = Timer::syst(cp.SYST, &rcc.clocks).counter_hz(); timer.start(1.Hz()).unwrap(); // Wait for the timer to trigger an update and change the state of the LED diff --git a/examples/nojtag.rs b/examples/nojtag.rs index b582ce7e..dd1ac79a 100644 --- a/examples/nojtag.rs +++ b/examples/nojtag.rs @@ -13,9 +13,10 @@ use stm32f1xx_hal::{pac, prelude::*}; fn main() -> ! { let p = pac::Peripherals::take().unwrap(); - let mut gpioa = p.GPIOA.split(); - let mut gpiob = p.GPIOB.split(); - let mut afio = p.AFIO.constrain(); + let mut rcc = p.RCC.constrain(); + let mut gpioa = p.GPIOA.split(&mut rcc); + let mut gpiob = p.GPIOB.split(&mut rcc); + let mut afio = p.AFIO.constrain(&mut rcc); let (pa15, pb3, pb4) = afio.mapr.disable_jtag(gpioa.pa15, gpiob.pb3, gpiob.pb4); diff --git a/examples/pwm.rs b/examples/pwm.rs index d15b899a..b229b00f 100644 --- a/examples/pwm.rs +++ b/examples/pwm.rs @@ -20,15 +20,12 @@ use stm32f1xx_hal::{ fn main() -> ! { let p = pac::Peripherals::take().unwrap(); - let mut flash = p.FLASH.constrain(); - let rcc = p.RCC.constrain(); + let mut rcc = p.RCC.constrain(); - let clocks = rcc.cfgr.freeze(&mut flash.acr); + let mut afio = p.AFIO.constrain(&mut rcc); - let mut afio = p.AFIO.constrain(); - - let mut gpioa = p.GPIOA.split(); - // let mut gpiob = p.GPIOB.split(); + let mut gpioa = p.GPIOA.split(&mut rcc); + // let mut gpiob = p.GPIOB.split(&mut rcc); // TIM2 let c1 = gpioa.pa0.into_alternate_push_pull(&mut gpioa.crl); @@ -51,11 +48,11 @@ fn main() -> ! { // let c4 = gpiob.pb9.into_alternate_push_pull(&mut gpiob.crh); //let mut pwm = - // Timer::new(p.TIM2, &clocks).pwm_hz::(pins, &mut afio.mapr, 1.kHz()); + // Timer::new(p.TIM2, &mut rcc).pwm_hz::(pins, &mut afio.mapr, 1.kHz()); // or let mut pwm = p .TIM2 - .pwm_hz::(pins, &mut afio.mapr, 1.kHz(), &clocks); + .pwm_hz::(pins, &mut afio.mapr, 1.kHz(), &mut rcc); // Enable clock on each of the channels pwm.enable(Channel::C1); diff --git a/examples/pwm_custom.rs b/examples/pwm_custom.rs index 95d3e2f0..654d4771 100644 --- a/examples/pwm_custom.rs +++ b/examples/pwm_custom.rs @@ -16,21 +16,18 @@ use cortex_m_rt::entry; fn main() -> ! { let p = pac::Peripherals::take().unwrap(); - let mut flash = p.FLASH.constrain(); - let rcc = p.RCC.constrain(); + let mut rcc = p.RCC.constrain(); - let clocks = rcc.cfgr.freeze(&mut flash.acr); - - let mut afio = p.AFIO.constrain(); - let gpioa = p.GPIOA.split(); - let mut gpiob = p.GPIOB.split(); + let mut afio = p.AFIO.constrain(&mut rcc); + let gpioa = p.GPIOA.split(&mut rcc); + let mut gpiob = p.GPIOB.split(&mut rcc); let (_pa15, _pb3, pb4) = afio.mapr.disable_jtag(gpioa.pa15, gpiob.pb3, gpiob.pb4); // TIM3 let p0 = pb4.into_alternate_push_pull(&mut gpiob.crl); let p1 = gpiob.pb5.into_alternate_push_pull(&mut gpiob.crl); - let pwm = Timer::new(p.TIM3, &clocks).pwm_hz((p0, p1), &mut afio.mapr, 1.kHz()); + let pwm = Timer::new(p.TIM3, &mut rcc).pwm_hz((p0, p1), &mut afio.mapr, 1.kHz()); let max = pwm.get_max_duty(); diff --git a/examples/pwm_input.rs b/examples/pwm_input.rs index e3987f0a..d41b5a11 100644 --- a/examples/pwm_input.rs +++ b/examples/pwm_input.rs @@ -7,22 +7,19 @@ use panic_halt as _; use cortex_m_rt::entry; -use stm32f1xx_hal::{pac, prelude::*, timer::pwm_input::*}; +use stm32f1xx_hal::{pac, prelude::*, rcc::BusTimerClock, timer::pwm_input::*}; #[entry] fn main() -> ! { let p = pac::Peripherals::take().unwrap(); - let mut flash = p.FLASH.constrain(); - let rcc = p.RCC.constrain(); + let mut rcc = p.RCC.constrain(); - let clocks = rcc.cfgr.freeze(&mut flash.acr); - - let mut afio = p.AFIO.constrain(); + let mut afio = p.AFIO.constrain(&mut rcc); let mut dbg = p.DBGMCU; - let gpioa = p.GPIOA.split(); - let gpiob = p.GPIOB.split(); + let gpioa = p.GPIOA.split(&mut rcc); + let gpiob = p.GPIOB.split(&mut rcc); let (_pa15, _pb3, pb4) = afio.mapr.disable_jtag(gpioa.pa15, gpiob.pb3, gpiob.pb4); let pb5 = gpiob.pb5; @@ -31,12 +28,13 @@ fn main() -> ! { (pb4, pb5), &mut dbg, Configuration::Frequency(10.kHz()), - &clocks, + &mut rcc, ); + let timer_clk = pac::TIM3::timer_clock(&rcc.clocks); loop { let _freq = pwm_input - .read_frequency(ReadMode::Instant, &clocks) + .read_frequency(ReadMode::Instant, timer_clk) .unwrap(); let _duty_cycle = pwm_input.read_duty(ReadMode::Instant).unwrap(); } diff --git a/examples/qei.rs b/examples/qei.rs index 266afd3b..9e301409 100644 --- a/examples/qei.rs +++ b/examples/qei.rs @@ -20,13 +20,10 @@ fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); let cp = cortex_m::Peripherals::take().unwrap(); - let mut flash = dp.FLASH.constrain(); - let rcc = dp.RCC.constrain(); + let mut rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.freeze(&mut flash.acr); - - // let gpioa = dp.GPIOA.split(); - let gpiob = dp.GPIOB.split(); + // let gpioa = dp.GPIOA.split(&mut rcc); + let gpiob = dp.GPIOB.split(&mut rcc); // TIM2 // let c1 = gpioa.pa0; @@ -40,8 +37,8 @@ fn main() -> ! { let c1 = gpiob.pb6; let c2 = gpiob.pb7; - let qei = Timer::new(dp.TIM4, &clocks).qei((c1, c2), QeiOptions::default()); - let mut delay = cp.SYST.delay(&clocks); + let qei = Timer::new(dp.TIM4, &mut rcc).qei((c1, c2), QeiOptions::default()); + let mut delay = cp.SYST.delay(&rcc.clocks); loop { let before = qei.count(); diff --git a/examples/rtc.rs b/examples/rtc.rs index 3b17bd56..7d310b69 100644 --- a/examples/rtc.rs +++ b/examples/rtc.rs @@ -18,8 +18,8 @@ fn main() -> ! { let p = pac::Peripherals::take().unwrap(); let mut pwr = p.PWR; - let rcc = p.RCC.constrain(); - let mut backup_domain = rcc.bkp.constrain(p.BKP, &mut pwr); + let mut rcc = p.RCC.constrain(); + let mut backup_domain = p.BKP.constrain(&mut pwr, &mut rcc); // Initializes rtc every startup, use only if you don't have a battery. // let rtc = Rtc::new(p.RTC, &mut backup_domain); @@ -30,7 +30,7 @@ fn main() -> ! { // due to unnecessary reinitialization of the crystal, // as well as reset of the selected frequency. // Else, the rtc is initialized. - let rtc = match Rtc::restore_or_new(p.RTC, &mut backup_domain) { + let rtc = match Rtc::restore_or_new(p.RTC, &mut backup_domain, &mut rcc) { Restored(rtc) => rtc, // The rtc is restored from previous configuration. You may verify the frequency you want if needed. New(mut rtc) => { // The rtc was just initialized, the clock source selected, frequency is 1.Hz() diff --git a/examples/serial-dma-circ.rs b/examples/serial-dma-circ.rs index bfe47ada..05ccaddc 100644 --- a/examples/serial-dma-circ.rs +++ b/examples/serial-dma-circ.rs @@ -21,16 +21,13 @@ use stm32f1xx_hal::{ fn main() -> ! { let p = pac::Peripherals::take().unwrap(); - let mut flash = p.FLASH.constrain(); - let rcc = p.RCC.constrain(); - - let clocks = rcc.cfgr.freeze(&mut flash.acr); + let mut rcc = p.RCC.constrain(); //let mut afio = p.AFIO.constrain(); - let channels = p.DMA1.split(); + let channels = p.DMA1.split(&mut rcc); - let mut gpioa = p.GPIOA.split(); - // let mut gpiob = p.GPIOB.split(); + let mut gpioa = p.GPIOA.split(&mut rcc); + // let mut gpiob = p.GPIOB.split(&mut rcc); // USART1 let tx = gpioa.pa9.into_alternate_push_pull(&mut gpioa.crh); @@ -52,7 +49,7 @@ fn main() -> ! { p.USART1, (tx, rx), Config::default().baudrate(9_600.bps()), - &clocks, + &mut rcc, ); let rx = serial.rx.with_dma(channels.5); diff --git a/examples/serial-dma-peek.rs b/examples/serial-dma-peek.rs index e0344f2d..8f3b025b 100644 --- a/examples/serial-dma-peek.rs +++ b/examples/serial-dma-peek.rs @@ -20,16 +20,13 @@ use stm32f1xx_hal::{ fn main() -> ! { let p = pac::Peripherals::take().unwrap(); - let mut flash = p.FLASH.constrain(); - let rcc = p.RCC.constrain(); - - let clocks = rcc.cfgr.freeze(&mut flash.acr); + let mut rcc = p.RCC.constrain(); //let mut afio = p.AFIO.constrain(); - let channels = p.DMA1.split(); + let channels = p.DMA1.split(&mut rcc); - let mut gpioa = p.GPIOA.split(); - // let mut gpiob = p.GPIOB.split(); + let mut gpioa = p.GPIOA.split(&mut rcc); + // let mut gpiob = p.GPIOB.split(&mut rcc); // USART1 let tx = gpioa.pa9.into_alternate_push_pull(&mut gpioa.crh); @@ -47,7 +44,7 @@ fn main() -> ! { // let tx = gpiob.pb10.into_alternate_push_pull(&mut gpiob.crh); // let rx = gpiob.pb11; - let serial = Serial::new(p.USART1, (tx, rx), Config::default(), &clocks); + let serial = Serial::new(p.USART1, (tx, rx), Config::default(), &mut rcc); let rx = serial.rx.with_dma(channels.5); let buf = singleton!(: [u8; 8] = [0; 8]).unwrap(); diff --git a/examples/serial-dma-rx.rs b/examples/serial-dma-rx.rs index cbdb7d52..9b65efb8 100644 --- a/examples/serial-dma-rx.rs +++ b/examples/serial-dma-rx.rs @@ -10,26 +10,19 @@ use panic_halt as _; use cortex_m::{asm, singleton}; use cortex_m_rt::entry; -use stm32f1xx_hal::{ - pac, - prelude::*, - serial::{Config, Serial}, -}; +use stm32f1xx_hal::{pac, prelude::*, serial::Serial}; #[entry] fn main() -> ! { let p = pac::Peripherals::take().unwrap(); - let mut flash = p.FLASH.constrain(); - let rcc = p.RCC.constrain(); + let mut rcc = p.RCC.constrain(); - let clocks = rcc.cfgr.freeze(&mut flash.acr); + //let mut afio = p.AFIO.constrain(&mut rcc); + let channels = p.DMA1.split(&mut rcc); - //let mut afio = p.AFIO.constrain(); - let channels = p.DMA1.split(); - - let mut gpioa = p.GPIOA.split(); - // let mut gpiob = p.GPIOB.split(); + let mut gpioa = p.GPIOA.split(&mut rcc); + // let mut gpiob = p.GPIOB.split(&mut rcc); // USART1 let tx = gpioa.pa9.into_alternate_push_pull(&mut gpioa.crh); @@ -47,12 +40,7 @@ fn main() -> ! { // let tx = gpiob.pb10.into_alternate_push_pull(&mut gpiob.crh); // let rx = gpiob.pb11; - let serial = Serial::new( - p.USART1, - (tx, rx), - Config::default().baudrate(9_600.bps()), - &clocks, - ); + let serial = Serial::new(p.USART1, (tx, rx), 9_600.bps(), &mut rcc); let rx = serial.rx.with_dma(channels.5); let buf = singleton!(: [u8; 8] = [0; 8]).unwrap(); diff --git a/examples/serial-dma-tx.rs b/examples/serial-dma-tx.rs index 575c3858..9ff7c1c0 100644 --- a/examples/serial-dma-tx.rs +++ b/examples/serial-dma-tx.rs @@ -20,16 +20,13 @@ use stm32f1xx_hal::{ fn main() -> ! { let p = pac::Peripherals::take().unwrap(); - let mut flash = p.FLASH.constrain(); - let rcc = p.RCC.constrain(); + let mut rcc = p.RCC.constrain(); - let clocks = rcc.cfgr.freeze(&mut flash.acr); + //let mut afio = p.AFIO.constrain(&mut rcc); + let channels = p.DMA1.split(&mut rcc); - //let mut afio = p.AFIO.constrain(); - let channels = p.DMA1.split(); - - let mut gpioa = p.GPIOA.split(); - // let mut gpiob = p.GPIOB.split(); + let mut gpioa = p.GPIOA.split(&mut rcc); + // let mut gpiob = p.GPIOB.split(&mut rcc); // USART1 let tx = gpioa.pa9.into_alternate_push_pull(&mut gpioa.crh); @@ -51,7 +48,7 @@ fn main() -> ! { p.USART1, (tx, rx), Config::default().baudrate(9600.bps()), - &clocks, + &mut rcc, ); let tx = serial.tx.with_dma(channels.4); diff --git a/examples/serial-fmt.rs b/examples/serial-fmt.rs index 8f5f0a11..ad3ae9b7 100644 --- a/examples/serial-fmt.rs +++ b/examples/serial-fmt.rs @@ -24,20 +24,13 @@ fn main() -> ! { // Get access to the device specific peripherals from the peripheral access crate let p = pac::Peripherals::take().unwrap(); - // Take ownership over the raw flash and rcc devices and convert them into the corresponding - // HAL structs - let mut flash = p.FLASH.constrain(); - let rcc = p.RCC.constrain(); - - // Freeze the configuration of all the clocks in the system and store the frozen frequencies in - // `clocks` - let clocks = rcc.cfgr.freeze(&mut flash.acr); + let mut rcc = p.RCC.constrain(); // Prepare the alternate function I/O registers //let mut afio = p.AFIO.constrain(); // Prepare the GPIOB peripheral - let mut gpiob = p.GPIOB.split(); + let mut gpiob = p.GPIOB.split(&mut rcc); // USART1 // let tx = gpioa.pa9.into_alternate_push_pull(&mut gpioa.crh); @@ -63,7 +56,7 @@ fn main() -> ! { p.USART3, (tx, rx), Config::default().baudrate(9600.bps()), - &clocks, + &mut rcc, ); // Split the serial struct into a receiving and a transmitting part diff --git a/examples/serial-interrupt-idle.rs b/examples/serial-interrupt-idle.rs index 2e4361e3..43095d86 100644 --- a/examples/serial-interrupt-idle.rs +++ b/examples/serial-interrupt-idle.rs @@ -21,20 +21,13 @@ fn main() -> ! { // Get access to the device specific peripherals from the peripheral access crate let p = pac::Peripherals::take().unwrap(); - // Take ownership over the raw flash and rcc devices and convert them into the corresponding - // HAL structs - let mut flash = p.FLASH.constrain(); - let rcc = p.RCC.constrain(); - - // Freeze the configuration of all the clocks in the system and store the frozen frequencies in - // `clocks` - let clocks = rcc.cfgr.freeze(&mut flash.acr); + let mut rcc = p.RCC.constrain(); // Prepare the alternate function I/O registers - let mut afio = p.AFIO.constrain(); + let mut afio = p.AFIO.constrain(&mut rcc); // Prepare the GPIOB peripheral - let mut gpiob = p.GPIOB.split(); + let mut gpiob = p.GPIOB.split(&mut rcc); // USART1 let tx = gpiob.pb6.into_alternate_push_pull(&mut gpiob.crl); @@ -45,7 +38,7 @@ fn main() -> ! { let (mut tx, mut rx) = p .USART1 .remap(&mut afio.mapr) - .serial((tx, rx), 115_200.bps(), &clocks) + .serial((tx, rx), 115_200.bps(), &mut rcc) .split(); tx.listen(); rx.listen(); diff --git a/examples/serial.rs b/examples/serial.rs index dd956c14..c3a21a19 100644 --- a/examples/serial.rs +++ b/examples/serial.rs @@ -21,20 +21,13 @@ fn main() -> ! { // Get access to the device specific peripherals from the peripheral access crate let p = pac::Peripherals::take().unwrap(); - // Take ownership over the raw flash and rcc devices and convert them into the corresponding - // HAL structs - let mut flash = p.FLASH.constrain(); - let rcc = p.RCC.constrain(); - - // Freeze the configuration of all the clocks in the system and store the frozen frequencies in - // `clocks` - let clocks = rcc.cfgr.freeze(&mut flash.acr); + let mut rcc = p.RCC.constrain(); // Prepare the alternate function I/O registers - //let mut afio = p.AFIO.constrain(); + //let mut afio = p.AFIO.constrain(&mut rcc); // Prepare the GPIOB peripheral - let mut gpiob = p.GPIOB.split(); + let mut gpiob = p.GPIOB.split(&mut rcc); // USART1 // let tx = gpioa.pa9.into_alternate_push_pull(&mut gpioa.crh); @@ -58,7 +51,7 @@ fn main() -> ! { // the registers are used to enable and configure the device. let mut serial = p .USART3 - .serial((tx, rx), Config::default().baudrate(115200.bps()), &clocks); + .serial((tx, rx), Config::default().baudrate(115200.bps()), &mut rcc); // Loopback test. Write `X` and wait until the write is successful. let sent = b'X'; diff --git a/examples/serial_9bits.rs b/examples/serial_9bits.rs index 26e00518..baffa555 100644 --- a/examples/serial_9bits.rs +++ b/examples/serial_9bits.rs @@ -99,20 +99,13 @@ fn main() -> ! { // Get access to the device specific peripherals from the peripheral access crate. let p = pac::Peripherals::take().unwrap(); - // Take ownership over the raw flash and rcc devices and convert them into the corresponding - // HAL structs. - let mut flash = p.FLASH.constrain(); - let rcc = p.RCC.constrain(); - - // Freeze the configuration of all the clocks in the system and store the frozen frequencies in - // `clocks`. - let clocks = rcc.cfgr.freeze(&mut flash.acr); + let mut rcc = p.RCC.constrain(); // Prepare the alternate function I/O registers. //let mut afio = p.AFIO.constrain(); // Prepare the GPIOB peripheral. - let gpiob = p.GPIOB.split(); + let gpiob = p.GPIOB.split(&mut rcc); let tx_pin = gpiob.pb10; let rx_pin = gpiob.pb11; @@ -128,7 +121,7 @@ fn main() -> ! { .baudrate(9600.bps()) .wordlength_9bits() .parity_none(), - &clocks, + &mut rcc, ); // Split the serial struct into a transmitting and a receiving part. diff --git a/examples/serial_config.rs b/examples/serial_config.rs index b0b1fc82..4c623757 100644 --- a/examples/serial_config.rs +++ b/examples/serial_config.rs @@ -21,20 +21,13 @@ fn main() -> ! { // Get access to the device specific peripherals from the peripheral access crate let p = pac::Peripherals::take().unwrap(); - // Take ownership over the raw flash and rcc devices and convert them into the corresponding - // HAL structs - let mut flash = p.FLASH.constrain(); - let rcc = p.RCC.constrain(); - - // Freeze the configuration of all the clocks in the system and store the frozen frequencies in - // `clocks` - let clocks = rcc.cfgr.freeze(&mut flash.acr); + let mut rcc = p.RCC.constrain(); // Prepare the alternate function I/O registers //let mut afio = p.AFIO.constrain(); // Prepare the GPIOB peripheral - let mut gpiob = p.GPIOB.split(); + let mut gpiob = p.GPIOB.split(&mut rcc); // USART1 // let tx = gpioa.pa9.into_alternate_push_pull(&mut gpioa.crh); @@ -59,7 +52,7 @@ fn main() -> ! { .stopbits(serial::StopBits::STOP2) .wordlength_9bits() .parity_odd(), - &clocks, + &mut rcc, ); let sent = b'U'; diff --git a/examples/serial_reconfigure.rs b/examples/serial_reconfigure.rs index cd4004d7..7a0d9cf8 100644 --- a/examples/serial_reconfigure.rs +++ b/examples/serial_reconfigure.rs @@ -25,20 +25,13 @@ fn main() -> ! { // Get access to the device specific peripherals from the peripheral access crate let p = pac::Peripherals::take().unwrap(); - // Take ownership over the raw flash and rcc devices and convert them into the corresponding - // HAL structs - let mut flash = p.FLASH.constrain(); - let rcc = p.RCC.constrain(); - - // Freeze the configuration of all the clocks in the system and store the frozen frequencies in - // `clocks` - let clocks = rcc.cfgr.freeze(&mut flash.acr); + let mut rcc = p.RCC.constrain(); // Prepare the alternate function I/O registers //let mut afio = p.AFIO.constrain(); // Prepare the GPIOB peripheral - let mut gpiob = p.GPIOB.split(); + let mut gpiob = p.GPIOB.split(&mut rcc); // USART1 // let tx = gpioa.pa9.into_alternate_push_pull(&mut gpioa.crh); @@ -64,7 +57,7 @@ fn main() -> ! { p.USART3, (tx, rx), Config::default().baudrate(9600.bps()), - &clocks, + &mut rcc, ); // Loopback test. Write `X` and wait until the write is successful. @@ -82,7 +75,7 @@ fn main() -> ! { // You can reconfigure the serial port to use a different baud rate at runtime. // This may block for a while if the transmission is still in progress. - block!(serial.reconfigure(Config::default().baudrate(115_200.bps()), &clocks)).unwrap(); + block!(serial.reconfigure(Config::default().baudrate(115_200.bps()), &rcc.clocks)).unwrap(); // Let's see if it works.' let sent = b'Y'; @@ -97,7 +90,7 @@ fn main() -> ! { &mut tx, &mut rx, Config::default().baudrate(9600.bps()), - &clocks + &rcc.clocks )) .unwrap(); diff --git a/examples/spi-dma.rs b/examples/spi-dma.rs index 1289c760..b8eef83e 100644 --- a/examples/spi-dma.rs +++ b/examples/spi-dma.rs @@ -18,17 +18,10 @@ fn main() -> ! { // Get access to the device specific peripherals from the peripheral access crate let dp = pac::Peripherals::take().unwrap(); - // Take ownership over the raw flash and rcc devices and convert them into the corresponding - // HAL structs - let mut flash = dp.FLASH.constrain(); - let rcc = dp.RCC.constrain(); - - // Freeze the configuration of all the clocks in the system and store the frozen frequencies in - // `clocks` - let clocks = rcc.cfgr.freeze(&mut flash.acr); + let mut rcc = dp.RCC.constrain(); // Acquire the GPIOB peripheral - let gpiob = dp.GPIOB.split(); + let gpiob = dp.GPIOB.split(&mut rcc); let pins = (Some(gpiob.pb13), Some(gpiob.pb14), Some(gpiob.pb15)); @@ -36,10 +29,10 @@ fn main() -> ! { polarity: Polarity::IdleLow, phase: Phase::CaptureOnFirstTransition, }; - let spi = Spi::new(dp.SPI2, pins, spi_mode, 100.kHz(), &clocks); + let spi = Spi::new(dp.SPI2, pins, spi_mode, 100.kHz(), &mut rcc); // Set up the DMA device - let dma = dp.DMA1.split(); + let dma = dp.DMA1.split(&mut rcc); // Connect the SPI device to the DMA let spi_dma = spi.with_tx_dma(dma.5); diff --git a/examples/spi-slave.rs b/examples/spi-slave.rs index a10e80b2..ec6f9bdd 100644 --- a/examples/spi-slave.rs +++ b/examples/spi-slave.rs @@ -31,13 +31,10 @@ static mut SPI2SLAVE: Option> = None; fn main() -> ! { let dp = Peripherals::take().unwrap(); - let mut flash = dp.FLASH.constrain(); - let rcc = dp.RCC.constrain(); + let mut rcc = dp.RCC.constrain(); - let clocks = rcc.cfgr.freeze(&mut flash.acr); - - let gpioa = dp.GPIOA.split(); - let gpiob = dp.GPIOB.split(); + let gpioa = dp.GPIOA.split(&mut rcc); + let gpiob = dp.GPIOB.split(&mut rcc); // SPI1 // Convert pins during SPI initialization @@ -45,9 +42,12 @@ fn main() -> ! { let miso = gpioa.pa6; let mosi = gpioa.pa7; - let spi1 = dp - .SPI1 - .spi((Some(sck), Some(miso), Some(mosi)), MODE, 10.kHz(), &clocks); + let spi1 = dp.SPI1.spi( + (Some(sck), Some(miso), Some(mosi)), + MODE, + 10.kHz(), + &mut rcc, + ); // SPI2 // Convert pins before SPI initialization @@ -55,10 +55,12 @@ fn main() -> ! { let miso = gpiob.pb14; let mosi = gpiob.pb15; - let spi2 = dp.SPI2.spi_slave((Some(sck), Some(miso), Some(mosi)), MODE); + let spi2 = dp + .SPI2 + .spi_slave((Some(sck), Some(miso), Some(mosi)), MODE, &mut rcc); // Set up the DMA device - let dma = dp.DMA1.split(); + let dma = dp.DMA1.split(&mut rcc); let master_spi_dma = spi1.with_rx_tx_dma(dma.2, dma.3); let slave_spi_dma = spi2.with_rx_tx_dma(dma.4, dma.5); diff --git a/examples/spi.rs b/examples/spi.rs index f4350fd0..1d04238f 100644 --- a/examples/spi.rs +++ b/examples/spi.rs @@ -21,13 +21,10 @@ use stm32f1xx_hal::{ fn setup() -> (Spi, PA4) { let dp = Peripherals::take().unwrap(); - let mut flash = dp.FLASH.constrain(); - let rcc = dp.RCC.constrain(); - - let clocks = rcc.cfgr.freeze(&mut flash.acr); + let mut rcc = dp.RCC.constrain(); //let mut afio = dp.AFIO.constrain(); - let mut gpioa = dp.GPIOA.split(); + let mut gpioa = dp.GPIOA.split(&mut rcc); // SPI1 let sck = gpioa.pa5; @@ -38,7 +35,7 @@ fn setup() -> (Spi, PA4) { let spi = dp .SPI1 //.remap(&mut afio.mapr) // if you want to use PB3, PB4, PB5 - .spi((Some(sck), Some(miso), Some(mosi)), MODE, 1.MHz(), &clocks); + .spi((Some(sck), Some(miso), Some(mosi)), MODE, 1.MHz(), &mut rcc); (spi, cs) } diff --git a/examples/timer-interrupt-rtic.rs b/examples/timer-interrupt-rtic.rs index 0c5df53a..1746bd12 100644 --- a/examples/timer-interrupt-rtic.rs +++ b/examples/timer-interrupt-rtic.rs @@ -31,17 +31,10 @@ mod app { #[init] fn init(cx: init::Context) -> (Shared, Local, init::Monotonics) { - // Take ownership over the raw flash and rcc devices and convert them into the corresponding - // HAL structs - let mut flash = cx.device.FLASH.constrain(); - let rcc = cx.device.RCC.constrain(); - - // Freeze the configuration of all the clocks in the system and store the frozen frequencies - // in `clocks` - let clocks = rcc.cfgr.freeze(&mut flash.acr); + let mut rcc = cx.device.RCC.constrain(); // Acquire the GPIOC peripheral - let mut gpioc = cx.device.GPIOC.split(); + let mut gpioc = cx.device.GPIOC.split(&mut rcc); // Configure gpio C pin 13 as a push-pull output. The `crh` register is passed to the // function in order to configure the port. For pins 0-7, crl should be passed instead @@ -49,7 +42,7 @@ mod app { .pc13 .into_push_pull_output_with_state(&mut gpioc.crh, PinState::High); // Configure the syst timer to trigger an update every second and enables interrupt - let mut timer = cx.device.TIM1.counter_ms(&clocks); + let mut timer = cx.device.TIM1.counter_ms(&mut rcc); timer.start(1.secs()).unwrap(); timer.listen(Event::Update); diff --git a/examples/usb_serial.rs b/examples/usb_serial.rs index cf3d49cb..782f5262 100644 --- a/examples/usb_serial.rs +++ b/examples/usb_serial.rs @@ -14,7 +14,7 @@ extern crate panic_semihosting; use cortex_m::asm::delay; use cortex_m_rt::entry; use stm32f1xx_hal::usb::{Peripheral, UsbBus}; -use stm32f1xx_hal::{pac, prelude::*}; +use stm32f1xx_hal::{pac, prelude::*, rcc}; use usb_device::prelude::*; use usbd_serial::{SerialPort, USB_CLASS_CDC}; @@ -23,23 +23,19 @@ fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); let mut flash = dp.FLASH.constrain(); - let rcc = dp.RCC.constrain(); + let mut rcc = dp.RCC.freeze( + rcc::Config::hse(8.MHz()).sysclk(48.MHz()).pclk1(24.MHz()), + &mut flash.acr, + ); - let clocks = rcc - .cfgr - .use_hse(8.MHz()) - .sysclk(48.MHz()) - .pclk1(24.MHz()) - .freeze(&mut flash.acr); - - assert!(clocks.usbclk_valid()); + assert!(rcc.clocks.usbclk_valid()); // Configure the on-board LED (PC13, green) - let mut gpioc = dp.GPIOC.split(); + let mut gpioc = dp.GPIOC.split(&mut rcc); let mut led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh); led.set_high(); // Turn off - let mut gpioa = dp.GPIOA.split(); + let mut gpioa = dp.GPIOA.split(&mut rcc); // BluePill board has a pull-up resistor on the D+ line. // Pull the D+ pin down to send a RESET condition to the USB bus. @@ -47,7 +43,7 @@ fn main() -> ! { // will not reset your device when you upload new firmware. let mut usb_dp = gpioa.pa12.into_push_pull_output(&mut gpioa.crh); usb_dp.set_low(); - delay(clocks.sysclk().raw() / 100); + delay(rcc.clocks.sysclk().raw() / 100); let usb = Peripheral { usb: dp.USB, diff --git a/examples/usb_serial_interrupt.rs b/examples/usb_serial_interrupt.rs index 9ece6a94..7d7e468e 100644 --- a/examples/usb_serial_interrupt.rs +++ b/examples/usb_serial_interrupt.rs @@ -7,9 +7,12 @@ extern crate panic_semihosting; use cortex_m::asm::{delay, wfi}; use cortex_m_rt::entry; -use stm32f1xx_hal::pac::{self, interrupt, Interrupt, NVIC}; -use stm32f1xx_hal::prelude::*; -use stm32f1xx_hal::usb::{Peripheral, UsbBus, UsbBusType}; +use stm32f1xx_hal::{ + pac::{self, interrupt, Interrupt, NVIC}, + prelude::*, + rcc, + usb::{Peripheral, UsbBus, UsbBusType}, +}; use usb_device::{bus::UsbBusAllocator, prelude::*}; use usbd_serial::{SerialPort, USB_CLASS_CDC}; @@ -22,18 +25,14 @@ fn main() -> ! { let dp = pac::Peripherals::take().unwrap(); let mut flash = dp.FLASH.constrain(); - let rcc = dp.RCC.constrain(); + let mut rcc = dp.RCC.freeze( + rcc::Config::hse(8.MHz()).sysclk(48.MHz()).pclk1(24.MHz()), + &mut flash.acr, + ); - let clocks = rcc - .cfgr - .use_hse(8.MHz()) - .sysclk(48.MHz()) - .pclk1(24.MHz()) - .freeze(&mut flash.acr); + assert!(rcc.clocks.usbclk_valid()); - assert!(clocks.usbclk_valid()); - - let mut gpioa = dp.GPIOA.split(); + let mut gpioa = dp.GPIOA.split(&mut rcc); // BluePill board has a pull-up resistor on the D+ line. // Pull the D+ pin down to send a RESET condition to the USB bus. @@ -41,7 +40,7 @@ fn main() -> ! { // will not reset your device when you upload new firmware. let mut usb_dp = gpioa.pa12.into_push_pull_output(&mut gpioa.crh); usb_dp.set_low(); - delay(clocks.sysclk().raw() / 100); + delay(rcc.clocks.sysclk().raw() / 100); let usb_dm = gpioa.pa11; let usb_dp = usb_dp.into_floating_input(&mut gpioa.crh); diff --git a/examples/usb_serial_rtic.rs b/examples/usb_serial_rtic.rs index b4d8ce3e..53e2a19f 100644 --- a/examples/usb_serial_rtic.rs +++ b/examples/usb_serial_rtic.rs @@ -10,8 +10,11 @@ use panic_semihosting as _; #[rtic::app(device = stm32f1xx_hal::pac)] mod app { use cortex_m::asm::delay; - use stm32f1xx_hal::prelude::*; - use stm32f1xx_hal::usb::{Peripheral, UsbBus, UsbBusType}; + use stm32f1xx_hal::{ + prelude::*, + rcc, + usb::{Peripheral, UsbBus, UsbBusType}, + }; use usb_device::prelude::*; #[shared] @@ -26,18 +29,14 @@ mod app { #[init(local = [usb_bus: Option> = None])] fn init(cx: init::Context) -> (Shared, Local, init::Monotonics) { let mut flash = cx.device.FLASH.constrain(); - let rcc = cx.device.RCC.constrain(); + let mut rcc = cx.device.RCC.freeze( + rcc::Config::hse(8.MHz()).sysclk(48.MHz()).pclk1(24.MHz()), + &mut flash.acr, + ); - let clocks = rcc - .cfgr - .use_hse(8.MHz()) - .sysclk(48.MHz()) - .pclk1(24.MHz()) - .freeze(&mut flash.acr); + assert!(rcc.clocks.usbclk_valid()); - assert!(clocks.usbclk_valid()); - - let mut gpioa = cx.device.GPIOA.split(); + let mut gpioa = cx.device.GPIOA.split(&mut rcc); // BluePill board has a pull-up resistor on the D+ line. // Pull the D+ pin down to send a RESET condition to the USB bus. @@ -45,7 +44,7 @@ mod app { // will not reset your device when you upload new firmware. let mut usb_dp = gpioa.pa12.into_push_pull_output(&mut gpioa.crh); usb_dp.set_low(); - delay(clocks.sysclk().raw() / 100); + delay(rcc.clocks.sysclk().raw() / 100); let usb_dm = gpioa.pa11; let usb_dp = usb_dp.into_floating_input(&mut gpioa.crh); diff --git a/src/adc.rs b/src/adc.rs index 1820438d..d7602cde 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -9,7 +9,7 @@ use fugit::HertzU32 as Hertz; use crate::dma::dma2; use crate::dma::{dma1, CircBuffer, Receive, RxDma, Transfer, TransferPayload, W}; use crate::gpio::{self, Analog}; -use crate::rcc::{Clocks, Enable, Reset}; +use crate::rcc::{Enable, Rcc, Reset}; use crate::time::kHz; use core::sync::atomic::{self, Ordering}; use cortex_m::asm::delay; @@ -206,12 +206,12 @@ impl Instance for pac::ADC3 { } pub trait AdcExt: Sized + Instance { - fn adc(self, clocks: &Clocks) -> Adc; + fn adc(self, rcc: &mut Rcc) -> Adc; } impl AdcExt for ADC { - fn adc(self, clocks: &Clocks) -> Adc { - Adc::new(self, clocks) + fn adc(self, rcc: &mut Rcc) -> Adc { + Adc::new(self, rcc) } } @@ -220,17 +220,17 @@ impl Adc { /// /// Sets all configurable parameters to one-shot defaults, /// performs a boot-time calibration. - pub fn new(adc: ADC, clocks: &Clocks) -> Self { + pub fn new(adc: ADC, rcc: &mut Rcc) -> Self { let mut s = Self { rb: adc, sample_time: SampleTime::default(), align: Align::default(), - sysclk: clocks.sysclk(), - adcclk: clocks.adcclk(), + sysclk: rcc.clocks.sysclk(), + adcclk: rcc.clocks.adcclk(), }; - s.enable_clock(); + s.enable_clock(rcc); s.power_down(); - s.reset(); + s.reset(rcc); s.setup_oneshot(); s.power_up(); @@ -308,18 +308,15 @@ impl Adc { self.rb.cr2().modify(|_, w| w.adon().clear_bit()); } - fn reset(&mut self) { - let rcc = unsafe { &(*RCC::ptr()) }; + fn reset(&mut self, rcc: &mut RCC) { ADC::reset(rcc); } - fn enable_clock(&mut self) { - let rcc = unsafe { &(*RCC::ptr()) }; + fn enable_clock(&mut self, rcc: &mut RCC) { ADC::enable(rcc); } - fn disable_clock(&mut self) { - let rcc = unsafe { &(*RCC::ptr()) }; + fn disable_clock(&mut self, rcc: &mut RCC) { ADC::disable(rcc); } @@ -439,9 +436,9 @@ impl Adc { } /// Powers down the ADC, disables the ADC clock and releases the ADC Peripheral - pub fn release(mut self) -> ADC { + pub fn release(mut self, rcc: &mut RCC) -> ADC { self.power_down(); - self.disable_clock(); + self.disable_clock(rcc); self.rb } diff --git a/src/afio.rs b/src/afio.rs index 8eb32b35..8ec619e1 100644 --- a/src/afio.rs +++ b/src/afio.rs @@ -7,12 +7,11 @@ use crate::gpio::{self, Alternate, Cr, Debugger, Floating, Input, OpenDrain, Pus use crate::sealed::Sealed; pub trait AfioExt { - fn constrain(self) -> Parts; + fn constrain(self, rcc: &mut RCC) -> Parts; } impl AfioExt for AFIO { - fn constrain(self) -> Parts { - let rcc = unsafe { &(*RCC::ptr()) }; + fn constrain(self, rcc: &mut RCC) -> Parts { AFIO::enable(rcc); AFIO::reset(rcc); diff --git a/src/can.rs b/src/can.rs index 980c3f05..c65da30c 100644 --- a/src/can.rs +++ b/src/can.rs @@ -25,10 +25,12 @@ pub trait CanExt: Sized + Instance { self, #[cfg(not(feature = "connectivity"))] usb: pac::USB, pins: (impl RInto, impl RInto, 0>), + rcc: &mut RCC, ) -> Can; fn can_loopback( self, #[cfg(not(feature = "connectivity"))] usb: pac::USB, + rcc: &mut RCC, ) -> Can; } @@ -37,22 +39,26 @@ impl CanExt for CAN { self, #[cfg(not(feature = "connectivity"))] usb: pac::USB, pins: (impl RInto, impl RInto, 0>), + rcc: &mut RCC, ) -> Can { Can::new( self, #[cfg(not(feature = "connectivity"))] usb, pins, + rcc, ) } fn can_loopback( self, #[cfg(not(feature = "connectivity"))] usb: pac::USB, + rcc: &mut RCC, ) -> Can { Can::new_loopback( self, #[cfg(not(feature = "connectivity"))] usb, + rcc, ) } } @@ -79,8 +85,8 @@ impl Rmp { self, #[cfg(not(feature = "connectivity"))] _usb: pac::USB, pins: (impl RInto, impl RInto, R>), + rcc: &mut RCC, ) -> Can { - let rcc = unsafe { &(*RCC::ptr()) }; CAN::enable(rcc); let pins = (Some(pins.0.rinto()), Some(pins.1.rinto())); @@ -89,11 +95,13 @@ impl Rmp { pub fn can_loopback( self, #[cfg(not(feature = "connectivity"))] usb: pac::USB, + rcc: &mut RCC, ) -> Can { Can::new_loopback( self.0, #[cfg(not(feature = "connectivity"))] usb, + rcc, ) } } @@ -107,11 +115,13 @@ impl Can { can: impl Into>, #[cfg(not(feature = "connectivity"))] _usb: pac::USB, pins: (impl RInto, impl RInto, R>), + rcc: &mut RCC, ) -> Can { can.into().can( #[cfg(not(feature = "connectivity"))] _usb, pins, + rcc, ) } @@ -119,8 +129,8 @@ impl Can { pub fn new_loopback( can: CAN, #[cfg(not(feature = "connectivity"))] _usb: pac::USB, + rcc: &mut RCC, ) -> Can { - let rcc = unsafe { &(*RCC::ptr()) }; CAN::enable(rcc); Can { diff --git a/src/crc.rs b/src/crc.rs index 85740342..367076c5 100644 --- a/src/crc.rs +++ b/src/crc.rs @@ -7,12 +7,11 @@ use crate::rcc::Enable; pub trait CrcExt { /// Constrains the CRC peripheral to play nicely with the other abstractions #[allow(clippy::wrong_self_convention, clippy::new_ret_no_self)] - fn new(self) -> Crc; + fn new(self, rcc: &mut RCC) -> Crc; } impl CrcExt for CRC { - fn new(self) -> Crc { - let rcc = unsafe { &(*RCC::ptr()) }; + fn new(self, rcc: &mut RCC) -> Crc { CRC::enable(rcc); Crc { crc: self } diff --git a/src/dac.rs b/src/dac.rs index 95c7d654..123a3629 100644 --- a/src/dac.rs +++ b/src/dac.rs @@ -49,12 +49,11 @@ impl Pins for (PA4, PA5) { } } -pub fn dac(_dac: DAC, _pins: PINS) -> PINS::Output +pub fn dac(_dac: DAC, _pins: PINS, rcc: &mut RCC) -> PINS::Output where PINS: Pins, { // Enable and reset clock. - let rcc = unsafe { &(*RCC::ptr()) }; DAC::enable(rcc); DAC::reset(rcc); @@ -85,17 +84,17 @@ macro_rules! dac { } pub trait DacExt { - fn constrain(self, pins: PINS) -> PINS::Output + fn constrain(self, pins: PINS, rcc: &mut RCC) -> PINS::Output where PINS: Pins; } impl DacExt for DAC { - fn constrain(self, pins: PINS) -> PINS::Output + fn constrain(self, pins: PINS, rcc: &mut RCC) -> PINS::Output where PINS: Pins, { - dac(self, pins) + dac(self, pins, rcc) } } diff --git a/src/dma.rs b/src/dma.rs index 4e7b6662..c90ac132 100644 --- a/src/dma.rs +++ b/src/dma.rs @@ -1,7 +1,7 @@ //! # Direct Memory Access #![allow(dead_code)] -use crate::pac; +use crate::pac::{self, RCC}; use core::{ convert::TryFrom, marker::PhantomData, @@ -54,7 +54,7 @@ where pub trait DmaExt: crate::Ptr { type Channels; - fn split(self) -> Self::Channels; + fn split(self, rcc: &mut RCC) -> Self::Channels; } pub trait TransferPayload { @@ -450,8 +450,7 @@ macro_rules! dma { impl DmaExt for $DMAX { type Channels = Channels; - fn split(self) -> Channels { - let rcc = unsafe { &(*RCC::ptr()) }; + fn split(self, rcc: &mut RCC) -> Channels { $DMAX::enable(rcc); // reset the DMA control registers (stops all on-going transfers) diff --git a/src/gpio.rs b/src/gpio.rs index b5790b6c..fead1c8b 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -77,7 +77,7 @@ use core::convert::Infallible; use core::marker::PhantomData; use crate::afio; -use crate::pac::EXTI; +use crate::pac::{EXTI, RCC}; mod partially_erased; pub use partially_erased::{PEPin, PartiallyErasedPin}; @@ -134,13 +134,13 @@ pub trait GpioExt { /// Splits the GPIO block into independent pins and registers. /// /// This resets the state of the GPIO block. - fn split(self) -> Self::Parts; + fn split(self, rcc: &mut RCC) -> Self::Parts; /// Splits the GPIO block into independent pins and registers without resetting its state. /// /// # Safety /// Make sure that all pins modes are set in reset state. - unsafe fn split_without_reset(self) -> Self::Parts; + unsafe fn split_without_reset(self, rcc: &mut RCC) -> Self::Parts; } /// Marker trait for active states. @@ -395,10 +395,9 @@ macro_rules! gpio { impl GpioExt for $GPIOX { type Parts = Parts; - fn split(self) -> Parts { - let rcc = unsafe { &(*RCC::ptr()) }; - $GPIOX::enable(rcc); - $GPIOX::reset(rcc); + fn split(self, rcc: &mut RCC) -> Parts { + $GPIOX::enable(rcc); + $GPIOX::reset(rcc); Parts { crl: Cr::<$port_id, false>, @@ -409,9 +408,8 @@ macro_rules! gpio { } } - unsafe fn split_without_reset(self) -> Parts { - let rcc = unsafe { &(*RCC::ptr()) }; - $GPIOX::enable(rcc); + unsafe fn split_without_reset(self, rcc: &mut RCC) -> Parts { + $GPIOX::enable(rcc); Parts { crl: Cr::<$port_id, false>, diff --git a/src/i2c.rs b/src/i2c.rs index 0711f217..7b9d4a2e 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -21,8 +21,8 @@ // https://www.st.com/content/ccc/resource/technical/document/application_note/5d/ae/a3/6f/08/69/4e/9b/CD00209826.pdf/files/CD00209826.pdf/jcr:content/translations/en.CD00209826.pdf use crate::afio::{self, RInto, Rmp}; -use crate::pac::{self, DWT, RCC}; -use crate::rcc::{BusClock, Clocks, Enable, Reset}; +use crate::pac::{self, DWT}; +use crate::rcc::{BusClock, Clocks, Enable, Rcc, Reset}; use crate::time::{kHz, Hertz}; use core::ops::Deref; @@ -106,7 +106,7 @@ pub trait I2cExt: Sized + Instance { self, pins: (impl RInto, impl RInto), mode: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> I2c; #[allow(clippy::too_many_arguments)] @@ -114,18 +114,18 @@ pub trait I2cExt: Sized + Instance { self, pins: (impl RInto, impl RInto), mode: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, start_timeout_us: u32, start_retries: u8, addr_timeout_us: u32, data_timeout_us: u32, ) -> BlockingI2c { - Self::i2c(self, pins, mode, clocks).blocking( + Self::i2c(self, pins, mode, rcc).blocking( start_timeout_us, start_retries, addr_timeout_us, data_timeout_us, - clocks, + &rcc.clocks, ) } } @@ -135,9 +135,9 @@ impl I2cExt for I2C { self, pins: (impl RInto, impl RInto), mode: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> I2c { - I2c::new(self, pins, mode, clocks) + I2c::new(self, pins, mode, rcc) } } @@ -168,9 +168,9 @@ impl I2c { i2c: impl Into>, pins: (impl RInto, impl RInto), mode: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Self { - i2c.into().i2c(pins, mode, clocks) + i2c.into().i2c(pins, mode, rcc) } } @@ -180,14 +180,13 @@ impl Rmp { self, pins: (impl RInto, impl RInto), mode: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> I2c { let mode = mode.into(); - let rcc = unsafe { &(*RCC::ptr()) }; I2C::enable(rcc); I2C::reset(rcc); - let pclk1 = I2C::clock(clocks); + let pclk1 = I2C::clock(&rcc.clocks); assert!(mode.get_frequency() <= kHz(400)); @@ -206,18 +205,18 @@ impl Rmp { self, pins: (impl RInto, impl RInto), mode: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, start_timeout_us: u32, start_retries: u8, addr_timeout_us: u32, data_timeout_us: u32, ) -> BlockingI2c { - self.i2c(pins, mode, clocks).blocking( + self.i2c(pins, mode, rcc).blocking( start_timeout_us, start_retries, addr_timeout_us, data_timeout_us, - clocks, + &rcc.clocks, ) } } diff --git a/src/i2c/blocking.rs b/src/i2c/blocking.rs index aa22a38c..6f580ec8 100644 --- a/src/i2c/blocking.rs +++ b/src/i2c/blocking.rs @@ -24,18 +24,18 @@ impl BlockingI2c { i2c: impl Into>, pins: (impl RInto, impl RInto), mode: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, start_timeout_us: u32, start_retries: u8, addr_timeout_us: u32, data_timeout_us: u32, ) -> Self { - I2c::new(i2c, pins, mode, clocks).blocking( + I2c::new(i2c, pins, mode, rcc).blocking( start_timeout_us, start_retries, addr_timeout_us, data_timeout_us, - clocks, + &rcc.clocks, ) } } diff --git a/src/prelude.rs b/src/prelude.rs index dcdb3c1c..59f86d96 100644 --- a/src/prelude.rs +++ b/src/prelude.rs @@ -17,6 +17,7 @@ pub use crate::gpio::GpioExt as _stm32_hal_gpio_GpioExt; pub use crate::hal_02::adc::OneShot as _embedded_hal_adc_OneShot; pub use crate::hal_02::prelude::*; pub use crate::i2c::I2cExt as _; +pub use crate::rcc::BkpExt as _; pub use crate::rcc::RccExt as _stm32_hal_rcc_RccExt; pub use crate::serial::SerialExt as _; pub use crate::spi::SpiExt as _; diff --git a/src/rcc.rs b/src/rcc.rs index 5fca1e03..32ebc691 100644 --- a/src/rcc.rs +++ b/src/rcc.rs @@ -1,6 +1,11 @@ //! # Reset & Control Clock -use crate::pac::{rcc, PWR, RCC}; +use core::ops::{Deref, DerefMut}; + +use crate::pac::{ + rcc::{self, RegisterBlock as RccRB}, + BKP, PWR, RCC, +}; use crate::flash::ACR; #[cfg(any(feature = "stm32f103", feature = "connectivity"))] @@ -15,23 +20,29 @@ mod enable; pub trait RccExt { /// Constrains the `RCC` peripheral so it plays nicely with the other abstractions fn constrain(self) -> Rcc; + + /// Constrains the `RCC` peripheral and apply clock configuration + fn freeze(self, rcc_cfg: Config, acr: &mut ACR) -> Rcc; + + /// Constrains the `RCC` peripheral and apply clock configuration + fn freeze_raw(self, rcc_cfg: RawConfig, acr: &mut ACR) -> Rcc; } impl RccExt for RCC { fn constrain(self) -> Rcc { Rcc { - cfgr: CFGR { - hse: None, - hse_bypass: false, - hclk: None, - pclk1: None, - pclk2: None, - sysclk: None, - adcclk: None, - }, - bkp: BKP, + rb: self, + clocks: Clocks::default(), } } + + fn freeze(self, rcc_cfg: Config, acr: &mut ACR) -> Rcc { + self.constrain().freeze(rcc_cfg, acr) + } + + fn freeze_raw(self, rcc_cfg: RawConfig, acr: &mut ACR) -> Rcc { + self.constrain().freeze_raw(rcc_cfg, acr) + } } /// Constrained RCC peripheral @@ -44,59 +55,54 @@ impl RccExt for RCC { /// let mut rcc = dp.RCC.constrain(); /// ``` pub struct Rcc { - pub cfgr: CFGR, - pub bkp: BKP, -} - -/// AMBA High-performance Bus (AHB) registers -#[non_exhaustive] -pub struct AHB; - -impl AHB { - fn enr(rcc: &rcc::RegisterBlock) -> &rcc::AHBENR { - rcc.ahbenr() - } + pub clocks: Clocks, + pub(crate) rb: RCC, } -/// Advanced Peripheral Bus 1 (APB1) registers -#[non_exhaustive] -pub struct APB1; - -impl APB1 { - fn enr(rcc: &rcc::RegisterBlock) -> &rcc::APB1ENR { - rcc.apb1enr() - } - - fn rstr(rcc: &rcc::RegisterBlock) -> &rcc::APB1RSTR { - rcc.apb1rstr() +impl Deref for Rcc { + type Target = RCC; + fn deref(&self) -> &Self::Target { + &self.rb } } -impl APB1 { - /// Set power interface clock (PWREN) bit in RCC_APB1ENR - pub fn set_pwren() { - let rcc = unsafe { &*RCC::ptr() }; - PWR::enable(rcc); +impl DerefMut for Rcc { + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.rb } } -/// Advanced Peripheral Bus 2 (APB2) registers -#[non_exhaustive] -pub struct APB2; +macro_rules! bus_struct { + ($($busX:ident => ($EN:ident, $en:ident, $($RST:ident, $rst:ident,)? $doc:literal),)+) => { + $( + #[doc = $doc] + #[non_exhaustive] + pub struct $busX; -impl APB2 { - fn enr(rcc: &rcc::RegisterBlock) -> &rcc::APB2ENR { - rcc.apb2enr() - } + impl $busX { + pub(crate) fn enr(rcc: &RccRB) -> &rcc::$EN { + rcc.$en() + } + $( + pub(crate) fn rstr(rcc: &RccRB) -> &rcc::$RST { + rcc.$rst() + } + )? + } + )+ + }; +} +use bus_struct; - fn rstr(rcc: &rcc::RegisterBlock) -> &rcc::APB2RSTR { - rcc.apb2rstr() - } +bus_struct! { + APB1 => (APB1ENR, apb1enr, APB1RSTR, apb1rstr, "Advanced Peripheral Bus 1 (APB1) registers"), + APB2 => (APB2ENR, apb2enr, APB2RSTR, apb2rstr, "Advanced Peripheral Bus 2 (APB2) registers"), + AHB => (AHBENR, ahbenr, "Advanced High-performance Bus (AHB) registers"), } const HSI: u32 = 8_000_000; // Hz -/// Clock configuration register (CFGR) +/// Clock configuration /// /// Used to configure the frequencies of the clocks present in the processor. /// @@ -106,7 +112,7 @@ const HSI: u32 = 8_000_000; // Hz /// **NOTE**: Currently, it is not guaranteed that the exact frequencies selected will be /// used, only frequencies close to it. #[derive(Debug, Default, PartialEq, Eq)] -pub struct CFGR { +pub struct Config { hse: Option, hse_bypass: bool, hclk: Option, @@ -116,7 +122,25 @@ pub struct CFGR { adcclk: Option, } -impl CFGR { +impl Config { + pub const DEFAULT: Self = Self { + hse: None, + hse_bypass: false, + hclk: None, + pclk1: None, + pclk2: None, + sysclk: None, + adcclk: None, + }; + + pub fn hsi() -> Self { + Self::DEFAULT + } + + pub fn hse(freq: Hertz) -> Self { + Self::DEFAULT.use_hse(freq) + } + /// Uses HSE (external oscillator) instead of HSI (internal RC oscillator) as the clock source. /// Will result in a hang if an external oscillator is not connected or it fails to start. /// The frequency specified must be the frequency of the external oscillator @@ -174,7 +198,9 @@ impl CFGR { self.adcclk = Some(freq.raw()); self } +} +impl Rcc { /// Applies the clock configuration and returns a `Clocks` struct that signifies that the /// clocks are frozen, and contains the frequencies used. After this function is called, /// the clocks can not change @@ -188,18 +214,13 @@ impl CFGR { /// let clocks = rcc.cfgr.freeze(&mut flash.acr); /// ``` #[inline(always)] - pub fn freeze(self, acr: &mut ACR) -> Clocks { - let cfg = Config::from_cfgr(self); - Self::_freeze_with_config(cfg, acr) + pub fn freeze(self, config: Config, acr: &mut ACR) -> Self { + let cfg = RawConfig::from_cfgr(config); + self.freeze_raw(cfg, acr) } #[inline(always)] - pub fn freeze_with_config(self, cfg: Config, acr: &mut ACR) -> Clocks { - Self::_freeze_with_config(cfg, acr) - } - - #[allow(unused_variables)] - fn _freeze_with_config(cfg: Config, acr: &mut ACR) -> Clocks { + pub fn freeze_raw(self, cfg: RawConfig, acr: &mut ACR) -> Self { let clocks = cfg.get_clocks(); // adjust flash wait states #[cfg(any(feature = "stm32f103", feature = "connectivity"))] @@ -247,89 +268,78 @@ impl CFGR { #[cfg(feature = "connectivity")] rcc.cfgr().modify(|_, w| unsafe { w.adcpre().variant(cfg.adcpre); - w.ppre2() - .bits(cfg.ppre2 as u8) - .ppre1() - .bits(cfg.ppre1 as u8) - .hpre() - .bits(cfg.hpre as u8) - .otgfspre() - .variant(cfg.usbpre) - .sw() - .bits(if cfg.pllmul.is_some() { - // PLL - 0b10 - } else if cfg.hse.is_some() { - // HSE - 0b1 - } else { - // HSI - 0b0 - }) + w.ppre2().bits(cfg.ppre2 as u8); + w.ppre1().bits(cfg.ppre1 as u8); + w.hpre().bits(cfg.hpre as u8); + w.otgfspre().variant(cfg.usbpre); + w.sw().bits(if cfg.pllmul.is_some() { + // PLL + 0b10 + } else if cfg.hse.is_some() { + // HSE + 0b1 + } else { + // HSI + 0b0 + }) }); #[cfg(feature = "stm32f103")] rcc.cfgr().modify(|_, w| unsafe { w.adcpre().variant(cfg.adcpre); - w.ppre2() - .bits(cfg.ppre2 as u8) - .ppre1() - .bits(cfg.ppre1 as u8) - .hpre() - .bits(cfg.hpre as u8) - .usbpre() - .variant(cfg.usbpre) - .sw() - .bits(if cfg.pllmul.is_some() { - // PLL - 0b10 - } else { - // HSE or HSI - u8::from(cfg.hse.is_some()) - }) + w.ppre2().bits(cfg.ppre2 as u8); + w.ppre1().bits(cfg.ppre1 as u8); + w.hpre().bits(cfg.hpre as u8); + w.usbpre().variant(cfg.usbpre); + w.sw().bits(if cfg.pllmul.is_some() { + // PLL + 0b10 + } else { + // HSE or HSI + u8::from(cfg.hse.is_some()) + }) }); #[cfg(any(feature = "stm32f100", feature = "stm32f101"))] rcc.cfgr().modify(|_, w| unsafe { w.adcpre().variant(cfg.adcpre); - w.ppre2() - .bits(cfg.ppre2 as u8) - .ppre1() - .bits(cfg.ppre1 as u8) - .hpre() - .bits(cfg.hpre as u8) - .sw() - .bits(if cfg.pllmul.is_some() { - // PLL - 0b10 - } else if cfg.hse.is_some() { - // HSE - 0b1 - } else { - // HSI - 0b0 - }) + w.ppre2().bits(cfg.ppre2 as u8); + w.ppre1().bits(cfg.ppre1 as u8); + w.hpre().bits(cfg.hpre as u8); + w.sw().bits(if cfg.pllmul.is_some() { + // PLL + 0b10 + } else if cfg.hse.is_some() { + // HSE + 0b1 + } else { + // HSI + 0b0 + }) }); - clocks + Self { + rb: self.rb, + clocks, + } } } -#[non_exhaustive] -pub struct BKP; - -impl BKP { +pub trait BkpExt { /// Enables write access to the registers in the backup domain - pub fn constrain(self, bkp: crate::pac::BKP, pwr: &mut PWR) -> BackupDomain { + fn constrain(self, pwr: &mut PWR, rcc: &mut RCC) -> BackupDomain; +} + +impl BkpExt for BKP { + fn constrain(self, pwr: &mut PWR, rcc: &mut RCC) -> BackupDomain { // Enable the backup interface by setting PWREN and BKPEN - let rcc = unsafe { &(*RCC::ptr()) }; - crate::pac::BKP::enable(rcc); - crate::pac::PWR::enable(rcc); + BKP::enable(rcc); + PWR::enable(rcc); // Enable access to the backup registers pwr.cr().modify(|_r, w| w.dbp().set_bit()); - BackupDomain { _regs: bkp } + BackupDomain { _regs: self } } } @@ -360,6 +370,23 @@ pub struct Clocks { usbclk_valid: bool, } +impl Default for Clocks { + fn default() -> Clocks { + let freq = HSI.Hz(); + Clocks { + hclk: freq, + pclk1: freq, + pclk2: freq, + ppre1: 1, + ppre2: 1, + sysclk: freq, + adcclk: freq / 2, + #[cfg(any(feature = "stm32f103", feature = "connectivity"))] + usbclk_valid: false, + } + } +} + impl Clocks { /// Returns the frequency of the AHB pub const fn hclk(&self) -> Hertz { @@ -483,16 +510,54 @@ pub trait RccBus: crate::Sealed { /// Enable/disable peripheral pub trait Enable: RccBus { - fn enable(rcc: &rcc::RegisterBlock); - fn disable(rcc: &rcc::RegisterBlock); + /// Enables peripheral + fn enable(rcc: &mut RCC); + + /// Disables peripheral + fn disable(rcc: &mut RCC); + + /// Check if peripheral enabled + fn is_enabled() -> bool; + + /// Check if peripheral disabled + #[inline] + fn is_disabled() -> bool { + !Self::is_enabled() + } + + /// # Safety + /// + /// Enables peripheral. Takes access to RCC internally + unsafe fn enable_unchecked() { + let mut rcc = RCC::steal(); + Self::enable(&mut rcc); + } + + /// # Safety + /// + /// Disables peripheral. Takes access to RCC internally + unsafe fn disable_unchecked() { + let mut rcc = RCC::steal(); + Self::disable(&mut rcc); + } } + /// Reset peripheral pub trait Reset: RccBus { - fn reset(rcc: &rcc::RegisterBlock); + /// Resets peripheral + fn reset(rcc: &mut RCC); + + /// # Safety + /// + /// Resets peripheral. Takes access to RCC internally + unsafe fn reset_unchecked() { + let mut rcc = RCC::steal(); + Self::reset(&mut rcc); + } } #[derive(Clone, Copy, Debug, PartialEq)] -pub struct Config { +pub struct RawConfig { pub hse: Option, pub hse_bypass: bool, pub pllmul: Option, @@ -505,7 +570,7 @@ pub struct Config { pub allow_overclock: bool, } -impl Default for Config { +impl Default for RawConfig { fn default() -> Self { Self { hse: None, @@ -566,8 +631,8 @@ pub type UsbPre = rcc::cfgr::USBPRE; pub type UsbPre = rcc::cfgr::OTGFSPRE; pub type AdcPre = rcc::cfgr::ADCPRE; -impl Config { - pub const fn from_cfgr(cfgr: CFGR) -> Self { +impl RawConfig { + pub const fn from_cfgr(cfgr: Config) -> Self { let hse = cfgr.hse; let hse_bypass = cfgr.hse_bypass; let pllsrcclk = if let Some(hse) = hse { hse } else { HSI / 2 }; @@ -746,13 +811,13 @@ impl Config { #[test] fn rcc_config_usb() { - let cfgr = CFGR::default() + let cfgr = Config::default() .use_hse(8.MHz()) .sysclk(48.MHz()) .pclk1(24.MHz()); - let config = Config::from_cfgr(cfgr); - let config_expected = Config { + let config = RawConfig::from_cfgr(cfgr); + let config_expected = RawConfig { hse: Some(8_000_000), hse_bypass: false, pllmul: Some(4), diff --git a/src/rcc/enable.rs b/src/rcc/enable.rs index 3f055748..b012b3e5 100644 --- a/src/rcc/enable.rs +++ b/src/rcc/enable.rs @@ -1,59 +1,55 @@ use super::*; use crate::bb; -macro_rules! bus { - ($($PER:ident => ($apbX:ty, $bit:literal),)+) => { - $( - impl RccBus for crate::pac::$PER { - type Bus = $apbX; - } - impl Enable for crate::pac::$PER { - #[inline(always)] - fn enable(rcc: &rcc::RegisterBlock) { - unsafe { - bb::set(Self::Bus::enr(rcc), $bit); - } +macro_rules! bus_enable { + ($PER:ident => $bit:literal) => { + impl Enable for crate::pac::$PER { + #[inline(always)] + fn enable(rcc: &mut RCC) { + unsafe { + bb::set(Self::Bus::enr(rcc), $bit); } - #[inline(always)] - fn disable(rcc: &rcc::RegisterBlock) { - unsafe { - bb::clear(Self::Bus::enr(rcc), $bit); - } + // Stall the pipeline to work around erratum 2.1.13 (DM00037591) + cortex_m::asm::dsb(); + } + #[inline(always)] + fn disable(rcc: &mut RCC) { + unsafe { + bb::clear(Self::Bus::enr(rcc), $bit); } } - impl Reset for crate::pac::$PER { - #[inline(always)] - fn reset(rcc: &rcc::RegisterBlock) { - unsafe { - bb::set(Self::Bus::rstr(rcc), $bit); - bb::clear(Self::Bus::rstr(rcc), $bit); - } + #[inline(always)] + fn is_enabled() -> bool { + let rcc = RCC::ptr(); + (Self::Bus::enr(unsafe { &*rcc }).read().bits() >> $bit) & 0x1 != 0 + } + } + }; +} + +macro_rules! bus_reset { + ($PER:ident => $bit:literal) => { + impl Reset for crate::pac::$PER { + #[inline(always)] + fn reset(rcc: &mut RCC) { + let rstr = Self::Bus::rstr(rcc); + unsafe { + bb::set(rstr, $bit); + bb::clear(rstr, $bit); } } - )+ - } + } + }; } -macro_rules! ahb_bus { - ($($PER:ident => ($bit:literal),)+) => { +macro_rules! bus { + ($($PER:ident => ($busX:ty, $bit:literal),)+) => { $( impl RccBus for crate::pac::$PER { - type Bus = AHB; - } - impl Enable for crate::pac::$PER { - #[inline(always)] - fn enable(rcc: &rcc::RegisterBlock) { - unsafe { - bb::set(Self::Bus::enr(rcc), $bit); - } - } - #[inline(always)] - fn disable(rcc: &rcc::RegisterBlock) { - unsafe { - bb::clear(Self::Bus::enr(rcc), $bit); - } - } + type Bus = $busX; } + bus_enable!($PER => $bit); + bus_reset!($PER => $bit); )+ } } @@ -110,16 +106,25 @@ bus! { SPI3 => (APB1, 15), } -ahb_bus! { - CRC => (6), - DMA1 => (0), - DMA2 => (1), +impl RccBus for crate::pac::CRC { + type Bus = AHB; } +bus_enable! { CRC => 6 } +impl RccBus for crate::pac::DMA1 { + type Bus = AHB; +} +bus_enable! { DMA1 => 0 } +impl RccBus for crate::pac::DMA2 { + type Bus = AHB; +} +bus_enable! { DMA2 => 1 } #[cfg(feature = "high")] -ahb_bus! { - FSMC => (8), +impl RccBus for crate::pac::FSMC { + type Bus = AHB; } +#[cfg(feature = "high")] +bus_enable! { FSMC => 8 } bus! { TIM2 => (APB1, 0), diff --git a/src/rtc.rs b/src/rtc.rs index b43442a2..54590e5b 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -62,13 +62,13 @@ impl Rtc { you may want to use [`restore_or_new`](Rtc::::restore_or_new) instead. */ - pub fn new(regs: RTC, bkp: &mut BackupDomain) -> Self { + pub fn new(regs: RTC, bkp: &mut BackupDomain, rcc: &mut RCC) -> Self { let mut result = Rtc { regs, _clock_source: PhantomData, }; - Self::enable_rtc(bkp); + Self::enable_rtc(bkp, rcc); // Set the prescaler to make it count up once every second. let prl = LSE_HERTZ.raw() - 1; @@ -97,9 +97,13 @@ impl Rtc { /// } /// }; /// ``` - pub fn restore_or_new(regs: RTC, bkp: &mut BackupDomain) -> RestoredOrNewRtc { + pub fn restore_or_new( + regs: RTC, + bkp: &mut BackupDomain, + rcc: &mut RCC, + ) -> RestoredOrNewRtc { if !Self::is_enabled() { - RestoredOrNewRtc::New(Rtc::new(regs, bkp)) + RestoredOrNewRtc::New(Rtc::new(regs, bkp, rcc)) } else { RestoredOrNewRtc::Restored(Rtc { regs, @@ -116,10 +120,7 @@ impl Rtc { } /// Enables the RTC device with the lse as the clock - fn enable_rtc(_bkp: &mut BackupDomain) { - // NOTE: Safe RCC access because we are only accessing bdcr - // and we have a &mut on BackupDomain - let rcc = unsafe { &*RCC::ptr() }; + fn enable_rtc(_bkp: &mut BackupDomain, rcc: &mut RCC) { rcc.bdcr().modify(|_, w| { // start the LSE oscillator w.lseon().set_bit(); diff --git a/src/serial.rs b/src/serial.rs index e67f16cb..a8d2e2e5 100644 --- a/src/serial.rs +++ b/src/serial.rs @@ -100,8 +100,8 @@ use crate::afio::{self, RInto, Rmp}; use crate::dma::dma2; use crate::dma::{self, dma1, CircBuffer, RxDma, Transfer, TxDma}; use crate::gpio::{Floating, PushPull, UpMode}; -use crate::pac::{self, RCC}; -use crate::rcc::{BusClock, Clocks, Enable, Reset}; +use crate::pac::{self}; +use crate::rcc::{BusClock, Clocks, Enable, Rcc, Reset}; use crate::time::{Bps, U32Ext}; mod hal_02; @@ -117,19 +117,19 @@ pub trait SerialExt: Sized + Instance { impl RInto, 0>, ), config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Serial; fn tx( self, tx_pin: impl RInto, 0>, config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Tx; fn rx( self, rx_pin: impl RInto, 0>, config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Rx; } @@ -141,25 +141,25 @@ impl SerialExt for USART { impl RInto, 0>, ), config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Serial { - Serial::new(self, pins, config, clocks) + Serial::new(self, pins, config, rcc) } fn tx( self, tx_pin: impl RInto, 0>, config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Tx { - Serial::tx(self, tx_pin, config, clocks) + Serial::tx(self, tx_pin, config, rcc) } fn rx( self, rx_pin: impl RInto, 0>, config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Rx { - Serial::rx(self, rx_pin, config, clocks) + Serial::rx(self, rx_pin, config, rcc) } } @@ -374,21 +374,21 @@ impl Rmp { impl RInto, R>, ), config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Serial { - Serial::_new(self.0, (Some(pins.0), Some(pins.1)), config, clocks) + Serial::_new(self.0, (Some(pins.0), Some(pins.1)), config, rcc) } pub fn tx( self, tx_pin: impl RInto, R>, config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Tx { Serial::_new( self.0, (Some(tx_pin), None::>), config, - clocks, + rcc, ) .split() .0 @@ -397,13 +397,13 @@ impl Rmp { self, rx_pin: impl RInto, R>, config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Rx { Serial::_new( self.0, (None::>, Some(rx_pin)), config, - clocks, + rcc, ) .split() .1 @@ -415,9 +415,9 @@ impl Serial { usart: impl Into>, tx_pin: impl RInto, R>, config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Tx { - usart.into().tx(tx_pin, config, clocks) + usart.into().tx(tx_pin, config, rcc) } } @@ -426,9 +426,9 @@ impl Serial { usart: impl Into>, rx_pin: impl RInto, R>, config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Rx { - usart.into().rx(rx_pin, config, clocks) + usart.into().rx(rx_pin, config, rcc) } } @@ -455,9 +455,9 @@ impl Serial { impl RInto, R>, ), config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Self { - usart.into().serial(pins, config, clocks) + usart.into().serial(pins, config, rcc) } fn _new( @@ -467,14 +467,13 @@ impl Serial { Option, R>>, ), config: impl Into, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Self { // Enable and reset USART - let rcc = unsafe { &(*RCC::ptr()) }; USART::enable(rcc); USART::reset(rcc); - apply_config::(config.into(), clocks); + apply_config::(config.into(), &rcc.clocks); let pins = (pins.0.map(RInto::rinto), pins.1.map(RInto::rinto)); @@ -520,7 +519,7 @@ impl Serial { /// Basic usage: /// /// ``` - /// let mut serial = Serial::new(usart, (tx_pin, rx_pin), &mut afio.mapr, 9600.bps(), &clocks); + /// let mut serial = Serial::new(usart, (tx_pin, rx_pin), &mut afio.mapr, 9600.bps(), &mut rcc); /// /// // You can split the `Serial` /// let Serial { tx, rx, token } = serial; diff --git a/src/spi.rs b/src/spi.rs index 4c404bf7..19d64d75 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -58,7 +58,7 @@ polarity: Polarity::IdleLow, phase: Phase::CaptureOnFirstTransition, }; - let spi = dp.SPI2.spi(pins, spi_mode, 100.khz(), &clocks); + let spi = dp.SPI2.spi(pins, spi_mode, 100.khz(), &mut rcc); ``` */ @@ -76,7 +76,7 @@ use crate::dma::dma1; use crate::dma::dma2; use crate::dma::{self, Receive, RxDma, RxTxDma, Transfer, TransferPayload, Transmit, TxDma}; use crate::gpio::{Floating, PushPull, UpMode}; -use crate::rcc::{BusClock, Clocks, Enable, Reset}; +use crate::rcc::{BusClock, Enable, Rcc, Reset}; use crate::time::Hertz; use core::sync::atomic::{self, Ordering}; @@ -150,7 +150,7 @@ pub trait SpiExt: Sized + Instance { ), mode: Mode, freq: Hertz, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Spi; fn spi_u16( self, @@ -161,9 +161,9 @@ pub trait SpiExt: Sized + Instance { ), mode: Mode, freq: Hertz, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Spi { - Self::spi(self, pins, mode, freq, clocks).frame_size_16bit() + Self::spi(self, pins, mode, freq, rcc).frame_size_16bit() } fn spi_slave( self, @@ -173,6 +173,7 @@ pub trait SpiExt: Sized + Instance { Option, 0>>, ), mode: Mode, + rcc: &mut RCC, ) -> SpiSlave; fn spi_slave_u16( self, @@ -182,8 +183,9 @@ pub trait SpiExt: Sized + Instance { Option, 0>>, ), mode: Mode, + rcc: &mut RCC, ) -> SpiSlave { - Self::spi_slave(self, pins, mode).frame_size_16bit() + Self::spi_slave(self, pins, mode, rcc).frame_size_16bit() } } @@ -197,9 +199,9 @@ impl SpiExt for SPI { ), mode: Mode, freq: Hertz, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Spi { - Spi::new(self, pins, mode, freq, clocks) + Spi::new(self, pins, mode, freq, rcc) } fn spi_slave( self, @@ -209,8 +211,9 @@ impl SpiExt for SPI { Option, 0>>, ), mode: Mode, + rcc: &mut RCC, ) -> SpiSlave { - SpiSlave::new(self, pins, mode) + SpiSlave::new(self, pins, mode, rcc) } } @@ -306,18 +309,17 @@ impl Rmp { ), mode: Mode, freq: Hertz, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Spi { let spi = self.0; // enable or reset SPI - let rcc = unsafe { &(*RCC::ptr()) }; SPI::enable(rcc); SPI::reset(rcc); // disable SS output spi.cr2().write(|w| w.ssoe().clear_bit()); - let br = match SPI::clock(clocks) / freq { + let br = match SPI::clock(&rcc.clocks) / freq { 0 => unreachable!(), 1..=2 => 0b000, 3..=5 => 0b001, @@ -374,9 +376,9 @@ impl Rmp { ), mode: Mode, freq: Hertz, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Spi { - self.spi(pins, mode, freq, clocks).frame_size_16bit() + self.spi(pins, mode, freq, rcc).frame_size_16bit() } pub fn spi_slave( self, @@ -386,10 +388,10 @@ impl Rmp { Option, R>>, ), mode: Mode, + rcc: &mut RCC, ) -> SpiSlave { let spi = self.0; // enable or reset SPI - let rcc = unsafe { &(*RCC::ptr()) }; SPI::enable(rcc); SPI::reset(rcc); @@ -438,8 +440,9 @@ impl Rmp { Option, R>>, ), mode: Mode, + rcc: &mut RCC, ) -> SpiSlave { - self.spi_slave(pins, mode).frame_size_16bit() + self.spi_slave(pins, mode, rcc).frame_size_16bit() } } @@ -460,9 +463,9 @@ impl Spi { ), mode: Mode, freq: Hertz, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Self { - spi.into().spi(pins, mode, freq, clocks) + spi.into().spi(pins, mode, freq, rcc) } } @@ -494,8 +497,9 @@ impl SpiSlave { Option, R>>, ), mode: Mode, + rcc: &mut RCC, ) -> Self { - spi.into().spi_slave(pins, mode) + spi.into().spi_slave(pins, mode, rcc) } } diff --git a/src/timer.rs b/src/timer.rs index b9e5d63a..a0e3b73d 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -49,9 +49,9 @@ #![allow(non_upper_case_globals)] use crate::bb; -use crate::pac::{self, DBGMCU as DBG, RCC}; +use crate::pac::{self, DBGMCU as DBG}; -use crate::rcc::{self, Clocks}; +use crate::rcc::{self, Clocks, Rcc}; use core::convert::TryFrom; use cortex_m::peripheral::syst::SystClkSource; use cortex_m::peripheral::SYST; @@ -116,51 +116,51 @@ pub enum Error { pub trait TimerExt: Sized { /// Non-blocking [Counter] with custom fixed precision - fn counter(self, clocks: &Clocks) -> Counter; + fn counter(self, rcc: &mut Rcc) -> Counter; /// Non-blocking [Counter] with fixed precision of 1 ms (1 kHz sampling) /// /// Can wait from 2 ms to 65 sec for 16-bit timer and from 2 ms to 49 days for 32-bit timer. /// /// NOTE: don't use this if your system frequency more than 65 MHz - fn counter_ms(self, clocks: &Clocks) -> CounterMs { - self.counter::<1_000>(clocks) + fn counter_ms(self, rcc: &mut Rcc) -> CounterMs { + self.counter::<1_000>(rcc) } /// Non-blocking [Counter] with fixed precision of 1 μs (1 MHz sampling) /// /// Can wait from 2 μs to 65 ms for 16-bit timer and from 2 μs to 71 min for 32-bit timer. - fn counter_us(self, clocks: &Clocks) -> CounterUs { - self.counter::<1_000_000>(clocks) + fn counter_us(self, rcc: &mut Rcc) -> CounterUs { + self.counter::<1_000_000>(rcc) } /// Non-blocking [Counter] with dynamic precision which uses `Hertz` as Duration units - fn counter_hz(self, clocks: &Clocks) -> CounterHz; + fn counter_hz(self, rcc: &mut Rcc) -> CounterHz; /// Blocking [Delay] with custom fixed precision - fn delay(self, clocks: &Clocks) -> Delay; + fn delay(self, rcc: &mut Rcc) -> Delay; /// Blocking [Delay] with fixed precision of 1 ms (1 kHz sampling) /// /// Can wait from 2 ms to 49 days. /// /// NOTE: don't use this if your system frequency more than 65 MHz - fn delay_ms(self, clocks: &Clocks) -> DelayMs { - self.delay::<1_000>(clocks) + fn delay_ms(self, rcc: &mut Rcc) -> DelayMs { + self.delay::<1_000>(rcc) } /// Blocking [Delay] with fixed precision of 1 μs (1 MHz sampling) /// /// Can wait from 2 μs to 71 min. - fn delay_us(self, clocks: &Clocks) -> DelayUs { - self.delay::<1_000_000>(clocks) + fn delay_us(self, rcc: &mut Rcc) -> DelayUs { + self.delay::<1_000_000>(rcc) } } impl TimerExt for TIM { - fn counter(self, clocks: &Clocks) -> Counter { - FTimer::new(self, clocks).counter() + fn counter(self, rcc: &mut Rcc) -> Counter { + FTimer::new(self, rcc).counter() } - fn counter_hz(self, clocks: &Clocks) -> CounterHz { - Timer::new(self, clocks).counter_hz() + fn counter_hz(self, rcc: &mut Rcc) -> CounterHz { + Timer::new(self, rcc).counter_hz() } - fn delay(self, clocks: &Clocks) -> Delay { - FTimer::new(self, clocks).delay() + fn delay(self, rcc: &mut Rcc) -> Delay { + FTimer::new(self, rcc).delay() } } @@ -583,17 +583,13 @@ macro_rules! with_pwm { impl Timer { /// Initialize timer - pub fn new(tim: TIM, clocks: &Clocks) -> Self { - unsafe { - //NOTE(unsafe) this reference will only be used for atomic writes with no side effects - let rcc = &(*RCC::ptr()); - // Enable and reset the timer peripheral - TIM::enable(rcc); - TIM::reset(rcc); - } + pub fn new(tim: TIM, rcc: &mut Rcc) -> Self { + // Enable and reset the timer peripheral + TIM::enable(rcc); + TIM::reset(rcc); Self { - clk: TIM::timer_clock(clocks), + clk: TIM::timer_clock(&rcc.clocks), tim, } } @@ -664,17 +660,13 @@ pub type FTimerMs = FTimer; impl FTimer { /// Initialize timer - pub fn new(tim: TIM, clocks: &Clocks) -> Self { - unsafe { - //NOTE(unsafe) this reference will only be used for atomic writes with no side effects - let rcc = &(*RCC::ptr()); - // Enable and reset the timer peripheral - TIM::enable(rcc); - TIM::reset(rcc); - } + pub fn new(tim: TIM, rcc: &mut Rcc) -> Self { + // Enable and reset the timer peripheral + TIM::enable(rcc); + TIM::reset(rcc); let mut t = Self { tim }; - t.configure(clocks); + t.configure(&rcc.clocks); t } diff --git a/src/timer/monotonic.rs b/src/timer/monotonic.rs index aebb5d02..9fec32f9 100644 --- a/src/timer/monotonic.rs +++ b/src/timer/monotonic.rs @@ -1,7 +1,7 @@ //! RTIC Monotonic implementation use super::{FTimer, Instance}; -use crate::rcc::Clocks; +use crate::rcc::Rcc; use core::ops::{Deref, DerefMut}; pub use fugit::{self, ExtU32}; use rtic_monotonic::Monotonic; @@ -37,17 +37,17 @@ impl MonoTimer { } pub trait MonoTimerExt: Sized { - fn monotonic(self, clocks: &Clocks) -> MonoTimer; - fn monotonic_us(self, clocks: &Clocks) -> MonoTimer { - self.monotonic::<1_000_000>(clocks) + fn monotonic(self, rcc: &mut Rcc) -> MonoTimer; + fn monotonic_us(self, rcc: &mut Rcc) -> MonoTimer { + self.monotonic::<1_000_000>(rcc) } } macro_rules! mono { ($TIM:ty) => { impl MonoTimerExt for $TIM { - fn monotonic(self, clocks: &Clocks) -> MonoTimer { - FTimer::new(self, clocks).monotonic() + fn monotonic(self, rcc: &mut Rcc) -> MonoTimer { + FTimer::new(self, rcc).monotonic() } } diff --git a/src/timer/pwm.rs b/src/timer/pwm.rs index 01fe1e61..4a102336 100644 --- a/src/timer/pwm.rs +++ b/src/timer/pwm.rs @@ -57,7 +57,7 @@ use crate::afio::MAPR; use crate::gpio::{self, Alternate}; use super::{compute_arr_presc, Channel, FTimer, Instance, Ocm, Timer, WithPwm}; -use crate::rcc::Clocks; +use crate::rcc::Rcc; use core::marker::PhantomData; use core::ops::{Deref, DerefMut}; use fugit::{HertzU32 as Hertz, TimerDurationU32}; @@ -137,7 +137,7 @@ where pins: PINS, mapr: &mut MAPR, time: TimerDurationU32, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Pwm where REMAP: Remap, @@ -148,7 +148,7 @@ where pins: PINS, mapr: &mut MAPR, freq: Hertz, - clocks: &Clocks, + rcc: &mut Rcc, ) -> PwmHz where REMAP: Remap, @@ -159,13 +159,13 @@ where pins: PINS, mapr: &mut MAPR, time: TimerDurationU32<1_000_000>, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Pwm where REMAP: Remap, PINS: Pins, { - self.pwm::<_, _, _, 1_000_000>(pins, mapr, time, clocks) + self.pwm::<_, _, _, 1_000_000>(pins, mapr, time, rcc) } } @@ -178,13 +178,13 @@ where pins: PINS, mapr: &mut MAPR, time: TimerDurationU32, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Pwm where REMAP: Remap, PINS: Pins, { - FTimer::::new(self, clocks).pwm(pins, mapr, time) + FTimer::::new(self, rcc).pwm(pins, mapr, time) } fn pwm_hz( @@ -192,13 +192,13 @@ where pins: PINS, mapr: &mut MAPR, time: Hertz, - clocks: &Clocks, + rcc: &mut Rcc, ) -> PwmHz where REMAP: Remap, PINS: Pins, { - Timer::new(self, clocks).pwm_hz(pins, mapr, time) + Timer::new(self, rcc).pwm_hz(pins, mapr, time) } } diff --git a/src/timer/pwm_input.rs b/src/timer/pwm_input.rs index df0d7d7a..59efac11 100644 --- a/src/timer/pwm_input.rs +++ b/src/timer/pwm_input.rs @@ -6,7 +6,7 @@ use crate::pac::{self, DBGMCU as DBG}; use crate::afio::{RInto, Rmp, TimC}; -use crate::rcc::{BusTimerClock, Clocks}; +use crate::rcc::Rcc; use crate::time::Hertz; use crate::timer::{General, Timer}; @@ -132,7 +132,7 @@ pub trait PwmInputExt: Sized + Instance { ), dbg: &mut DBG, mode: Configuration, - clocks: &Clocks, + rcc: &mut Rcc, ) -> PwmInput; } @@ -144,7 +144,7 @@ pub trait QeiExt: Sized + Instance { impl RInto<>::In, 0>, ), options: QeiOptions, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Qei; } @@ -194,9 +194,9 @@ macro_rules! hal { ), dbg: &mut DBG, mode: Configuration, - clocks: &Clocks, + rcc: &mut Rcc, ) -> PwmInput { - Timer::new(self, clocks).pwm_input(pins, dbg, mode) + Timer::new(self, rcc).pwm_input(pins, dbg, mode) } } impl QeiExt for $TIM { @@ -207,9 +207,9 @@ macro_rules! hal { impl RInto<>::In, 0>, ), options: QeiOptions, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Qei { - Timer::new(self, clocks).qei(pins, options) + Timer::new(self, rcc).qei(pins, options) } } @@ -222,9 +222,9 @@ macro_rules! hal { ), dbg: &mut DBG, mode: Configuration, - clocks: &Clocks, + rcc: &mut Rcc, ) -> PwmInput<$TIM> { - let mut tim = Timer::new(self.0, clocks); + let mut tim = Timer::new(self.0, rcc); tim.stop_in_debug(dbg, false); let Timer { tim, clk } = tim; $timX(tim, pins, clk, mode) @@ -236,9 +236,9 @@ macro_rules! hal { impl RInto<<$TIM as TimC<1>>::In, R>, ), options: QeiOptions, - clocks: &Clocks, + rcc: &mut Rcc, ) -> Qei<$TIM> { - let Timer { tim, clk: _ } = Timer::new(self.0, clocks); + let Timer { tim, clk: _ } = Timer::new(self.0, rcc); $qeix(tim, pins, options) } } @@ -321,7 +321,7 @@ macro_rules! hal { impl PwmInput<$TIM> { /// Return the frequency sampled by the timer - pub fn read_frequency(&self, mode: ReadMode, clocks: &Clocks) -> Result { + pub fn read_frequency(&self, mode: ReadMode, clk: Hertz) -> Result { if let ReadMode::WaitForNextCapture = mode { self.wait_for_capture(); } @@ -346,7 +346,6 @@ macro_rules! hal { if ccr1 == 0 { Err(Error::FrequencyTooLow) } else { - let clk = <$TIM>::timer_clock(&clocks); Ok(clk / ((presc + 1) as u32 * (ccr1 + 1) as u32)) } } diff --git a/src/usb.rs b/src/usb.rs index 1059158f..77a15d13 100644 --- a/src/usb.rs +++ b/src/usb.rs @@ -4,7 +4,7 @@ //! See //! for usage examples. -use crate::pac::{RCC, USB}; +use crate::pac::USB; use crate::rcc::{Enable, Reset}; use stm32_usbd::UsbPeripheral; @@ -29,12 +29,10 @@ unsafe impl UsbPeripheral for Peripheral { fn enable() { unsafe { - let rcc = &*RCC::ptr(); - // Enable USB peripheral - USB::enable(rcc); + USB::enable_unchecked(); // Reset USB peripheral - USB::reset(rcc); + USB::reset_unchecked(); } }