treewide: fix many typos

Author: newAM

.config/lingo.dic

@@ -0,0 +1,136 @@
+100
+AES
+AHB
+autoreload
+bitmask
+bitrate
+BPSK
+brainpool
+BT
+codebook
+COMP1_OUT
+COMP2_OUT
+CRC
+cryptographically
+D0
+D5
+DAC
+datasheet
+dBm
+decrypt
+despreading
+detections
+DMA
+DMA1
+DMA2
+DMAMUX
+DS13293
+durations
+ECB
+ECC
+ECDSA
+EXTI
+fn
+FS
+FSK
+Functionalities
+GCM
+GFSK
+GPIO
+GPIOA
+GPIOB
+GPIOs
+hal
+HALs
+HCLK3
+HSE
+HSE32
+HSI
+HW
+IEEE
+IRQ
+IRQs
+ISR
+jitter
+kibibytes
+LED1
+LED2
+LED3
+LEDs
+LoRa
+LPTIM
+LPTIM_ICR
+LPTIM_ISR
+LPTIM1
+LPTIM1_OUT
+LPTIM2
+LPTIM2_OUT
+LPTIM3
+LPUART
+LSE
+LSI
+mA
+milliamps
+millivolts
+MISO
+MOSI
+MSI
+MSK
+mV
+nist
+NSS
+NUCLEO
+NVIC
+opcode
+PB3
+pF
+PKA
+PLL
+pointee
+prescaler
+prescalers
+PWM
+Quickstart
+ramping
+RM0453
+RNG
+RSA
+RSSI
+RTC
+runtime
+SCK
+seeed
+SMPS
+SNR
+SPI
+SRAM
+startup
+STM32WL
+STM32WL5X
+struct
+subghz
+SubGhz
+SubGHz
+SUBGHZ
+syncword
+sysclk
+systick
+TAMP1
+TAMP2
+TAMP3
+TCXO
+timestamp
+Timestamp
+tuple
+TXCO
+UART
+UFBGA73
+UFQFPN48
+UID64
+uncalibrated
+unmapped
+VBAT
+wakeup
+WFE
+WFI
+WLCSP59

.config/spellcheck.toml

@@ -0,0 +1,9 @@
+# see https://github.com/drahnr/cargo-spellcheck
+[Hunspell]
+lang = "en_US"
+
+search_dirs = ["."]
+extra_dictionaries = ["lingo.dic"]
+
+skip_os_lookups = true
+use_builtin = true

hal/src/aes.rs

@@ -132,10 +132,10 @@ impl From<Aes> for AesWrapClk {
 #[derive(Debug, PartialEq, Eq, Clone, Copy)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Error {
-    /// Unexpected read operation from the AES_DOUTR register
+    /// Unexpected read operation from the `AES_DOUTR` register
     /// during computation or data input phase.
     Read,
-    /// Unexpected write operation to the AES_DINR register
+    /// Unexpected write operation to the `AES_DINR` register
     /// during computation or data output phase.
     Write,
 }

hal/src/dma/cr.rs

@@ -63,7 +63,7 @@ impl Cr {
 
     /// Reset value + DMA disabled.
     ///
-    /// This is eqivalent to the reset value, it is provided to make the code
+    /// This is equivalent to the reset value, it is provided to make the code
     /// more expressive.
     ///
     /// # Example
@@ -100,7 +100,7 @@ impl Cr {
         self.val
     }
 
-    /// Set the priviledged mode bit.
+    /// Set the privileged mode bit.
     ///
     /// This bit can only be set and cleared by a privileged software.
     ///
@@ -302,7 +302,7 @@ impl Cr {
     ///
     /// Note: The memory-to-memory mode must not be used in circular mode.
     /// Before enabling a channel in memory-to-memory mode, the software must
-    /// clear the CIRC bit of the DMA_CCRx register.
+    /// clear the `CIRC` bit of the `DMA_CCRx` register.
     ///
     /// **Note:** This field is set and cleared by software
     /// (privileged/secure software if the channel is in privileged/secure mode).
@@ -592,10 +592,10 @@ impl Cr {
 
     /// Set the circular mode bit.
     ///
-    /// In circular mode, after the last data transfer, the DMA_CNDTRx register
+    /// In circular mode, after the last data transfer, the `DMA_CNDTRx` register
     /// is automatically reloaded with the initially programmed value.
     /// The current internal address registers are reloaded with the base
-    /// address values from the DMA_CPARx and DMA_CMARx registers.
+    /// address values from the `DMA_CPARx` and `DMA_CMARx` registers.
     ///
     /// # Example
     ///
@@ -644,7 +644,7 @@ impl Cr {
         self.set_dir(Dir::FromMem)
     }
 
-    /// Set the transfer direction from peipheral.
+    /// Set the transfer direction from peripheral.
     ///
     /// # Example
     ///

hal/src/dma/mod.rs

@@ -27,7 +27,7 @@ pub mod flags {
     pub const GLOBAL: u8 = 1 << 0;
     /// Transfer complete.
     pub const XFER_CPL: u8 = 1 << 1;
-    /// Transfer hald complete.
+    /// Transfer half complete.
     pub const XFER_HLF: u8 = 1 << 2;
     /// Transfer error.
     pub const XFER_ERR: u8 = 1 << 3;
@@ -549,7 +549,7 @@ impl Dma1 {
     /// This will enable clocks and reset the DMA1 and DMAMUX peripherals.
     ///
     /// Most of the time you will want to use [`AllDma::split`].
-    /// This is provided for low-power usecases where you do not need
+    /// This is provided for low-power use cases where you do not need
     /// both DMA controllers.
     ///
     /// # Example

hal/src/flash.rs

@@ -618,7 +618,7 @@ impl<'a> Flash<'a> {
     /// 1. Do not write to flash memory that is being used for your code.
     /// 2. The destination address must be within the flash memory region.
     /// 3. The `from` and `to` pointers must be aligned to `u64`.
-    ///    Use `#[repr(align(8))]` to align your stucture.
+    ///    Use `#[repr(align(8))]` to align your structure.
     #[allow(unused_unsafe)]
     pub unsafe fn standard_program_generic<T>(
         &mut self,

hal/src/gpio.rs

@@ -376,7 +376,7 @@ pub trait Exti {
     /// [`gpio-button-irq.rs`]: https://github.com/stm32-rs/stm32wlxx-hal/blob/main/examples/examples/gpio-button-irq.rs
     fn clear_exti();
 
-    /// Returns true if a trigger request occured.
+    /// Returns true if a trigger request occurred.
     ///
     /// # Example
     ///

hal/src/lptim/cfgr.rs

@@ -154,7 +154,7 @@ impl Cfgr {
     /// ```
     pub const RESET: Cfgr = Cfgr::new(0);
 
-    /// Cfgreate a new Cfgr register from a raw value.
+    /// Create a new `Cfgr` register from a raw value.
     ///
     /// # Example
     ///

hal/src/lptim/mod.rs

@@ -52,7 +52,7 @@ pub mod irq {
     /// Set by hardware when the APB bus write to the RCR register has been
     /// successfully completed.
     pub const REPOK: u32 = 1 << 8;
-    /// Update event occured.
+    /// Update event occurred.
     pub const UE: u32 = 1 << 7;
     /// Counter direction change up to down.
     ///
@@ -286,7 +286,7 @@ paste_lptim!(3);
 
 /// Low-power timer trait.
 pub trait LpTim: sealed::LpTim {
-    /// Tigger selection options.
+    /// Trigger selection options.
     type TrgSel: Into<u32>;
 
     /// Create a new LPTIM driver.

hal/src/pka.rs

@@ -331,7 +331,7 @@ impl Pka {
     /// 2. You cannot use the PKA bus while the clock is disabled.
     /// 3. You are responsible for re-enabling the clock before resuming use
     ///    of the PKA bus.
-    /// 4. You are reponsible for setting up anything that may have lost state
+    /// 4. You are responsible for setting up anything that may have lost state
     ///    while the clock was disabled.
     #[inline]
     pub unsafe fn disable_clock(rcc: &mut pac::RCC) {
@@ -350,7 +350,7 @@ impl Pka {
     /// # Safety
     ///
     /// 1. The PKA must not be in-use.
-    /// 2. You are reponsible for setting up the PKA after a reset.
+    /// 2. You are responsible for setting up the PKA after a reset.
     #[inline]
     pub unsafe fn pulse_reset(rcc: &mut pac::RCC) {
         rcc.ahb3rstr.modify(|_, w| w.pkarst().set_bit());
@@ -420,7 +420,7 @@ impl Pka {
         });
     }
 
-    /// ECDSA (Ellipctic Curve Digital Signature Algorithm) signing.
+    /// ECDSA (Elliptic Curve Digital Signature Algorithm) signing.
     ///
     /// This is the blocking ECDSA sign method, equivalent to calling
     /// [`ecdsa_sign_start`](Self::ecdsa_sign_start) then polling
@@ -552,7 +552,7 @@ impl Pka {
         }
     }
 
-    /// ECDSA (Ellipctic Curve Digital Signature Algorithm) verification.
+    /// ECDSA (Elliptic Curve Digital Signature Algorithm) verification.
     ///
     /// This is the blocking ECDSA verify method, equivalent to calling
     /// [`ecdsa_verify_start`](Self::ecdsa_verify_start) then polling