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Commit 169d598

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DanieleParraviciniDanieleParravicini
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Removed unused modules and update AXI_top_tb
1 parent acc1eaa commit 169d598

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6 files changed

+82
-1050
lines changed

6 files changed

+82
-1050
lines changed

‎rtl_src/basic_block.sv

Lines changed: 74 additions & 127 deletions
Original file line numberDiff line numberDiff line change
@@ -43,24 +43,23 @@ module basic_block #(
4343
localparam I_WIDTH = 16;
4444
localparam OFFSET_I= $clog2(MEMORY_WIDTH/I_WIDTH);
4545
localparam CPU_MEMORY_ADDR_WIDTH = MEMORY_ADDR_WIDTH+OFFSET_I;
46-
//output latency is unused by basic block.
46+
4747
wire [LATENCY_COUNT_WIDTH-1:0] output_pc_latency_unused;
4848
assign output_pc_latency_unused = output_pc_latency;
49-
//sub signals of input_pc_and_current, output_pc_and_current
49+
5050
logic [PC_WIDTH-1:0] output_pc, input_pc;
5151
logic input_pc_is_directed_to_current, output_pc_is_directed_to_current;
52-
//signals for regex_cpu
52+
5353
logic regex_cpu_running ;
5454
logic regex_cpu_input_pc_ready,regex_cpu_input_pc_valid;
5555
localparam REGEX_CPU_FIFO_WIDTH_POWER_OF_2 = 2;
5656
logic [REGEX_CPU_FIFO_WIDTH_POWER_OF_2:0] regex_cpu_latency;
57-
//storage part of the basic block
58-
//cache wires
57+
5958
wire regex_cpu_memory_ready ;
6059
wire [CPU_MEMORY_ADDR_WIDTH-1:0]regex_cpu_memory_addr ;
6160
wire [I_WIDTH-1 :0] regex_cpu_memory_data ;
6261
wire regex_cpu_memory_valid ;
63-
//FIFO even signal
62+
6463
logic fifo_even_data_in_ready ;
6564
logic fifo_even_data_in_not_ready ;
6665
logic [PC_WIDTH-1:0] fifo_even_data_in ;
@@ -70,7 +69,7 @@ module basic_block #(
7069
logic fifo_even_data_out_valid ;
7170
logic fifo_even_data_out_not_valid;
7271
logic [FIFO_COUNT_WIDTH-1:0]fifo_even_data_count ;
73-
//FIFO odd signal
72+
7473
logic fifo_odd_data_in_ready ;
7574
logic fifo_odd_data_in_not_ready ;
7675
logic [PC_WIDTH-1:0] fifo_odd_data_in ;
@@ -80,15 +79,15 @@ module basic_block #(
8079
logic fifo_odd_data_out_valid ;
8180
logic fifo_odd_data_out_not_valid ;
8281
logic [FIFO_COUNT_WIDTH-1:0]fifo_odd_data_count ;
83-
//FIFO cur_char signal
82+
8483
logic fifo_cur_char_data_in_ready ;
8584
logic [PC_WIDTH-1:0] fifo_cur_char_data_in ;
8685
logic fifo_cur_char_data_in_valid ;
8786
logic fifo_cur_char_data_out_ready ;
8887
logic [PC_WIDTH-1:0] fifo_cur_char_data_out ;
8988
logic fifo_cur_char_data_out_valid ;
9089
logic [FIFO_COUNT_WIDTH-1:0]fifo_cur_char_data_count ;
91-
//FIFO next_char signal
90+
9291
logic fifo_next_char_data_in_ready ;
9392
logic [PC_WIDTH-1:0] fifo_next_char_data_in ;
9493
logic fifo_next_char_data_in_valid ;
@@ -97,49 +96,46 @@ module basic_block #(
9796
logic fifo_next_char_data_out_valid;
9897
logic [FIFO_COUNT_WIDTH-1:0]fifo_next_char_data_count ;
9998

100-
//FIFO even instantiation
99+
101100
fifo #(
102101
.DWIDTH(PC_WIDTH),
103102
.COUNT_WIDTH(FIFO_COUNT_WIDTH)
104103
)fifo_even(
105104
.clk (clk ),
106105
.reset (reset ),
107-
.full (fifo_even_data_in_not_ready ), //equivalent to not data_in_ready
106+
.full (fifo_even_data_in_not_ready ),
108107
.din (fifo_even_data_in ),
109-
.wr_en (fifo_even_data_in_valid ), //equivalent to data_in_valid
110-
.rd_en (fifo_even_data_out_ready ), //equivalent to data_out_ready
108+
.wr_en (fifo_even_data_in_valid ),
109+
.rd_en (fifo_even_data_out_ready ),
111110
.dout (fifo_even_data_out ),
112-
.empty (fifo_even_data_out_not_valid), //equivalent to not data_out_valid
111+
.empty (fifo_even_data_out_not_valid),
113112
.data_count (fifo_even_data_count )
114113
);
115-
//conclusion fifo even instatiation convert negated not_ready/not_valid signals to "standard" ready/valid interface.
116114
assign fifo_even_data_in_ready = ~ fifo_even_data_in_not_ready ;
117115
assign fifo_even_data_out_valid = ~ fifo_even_data_out_not_valid;
118116

119-
//FIFO odd instantiation
117+
120118
fifo #(
121119
.DWIDTH(PC_WIDTH),
122120
.COUNT_WIDTH(FIFO_COUNT_WIDTH)
123121
)fifo_odd(
124122
.clk (clk ),
125123
.reset (reset ),
126-
.full (fifo_odd_data_in_not_ready ), //equivalent to not data_in_ready
124+
.full (fifo_odd_data_in_not_ready ),
127125
.din (fifo_odd_data_in ),
128-
.wr_en (fifo_odd_data_in_valid ), //equivalent to data_in_valid
129-
.rd_en (fifo_odd_data_out_ready ), //equivalent to data_out_ready
126+
.wr_en (fifo_odd_data_in_valid ),
127+
.rd_en (fifo_odd_data_out_ready ),
130128
.dout (fifo_odd_data_out ),
131129
.data_count (fifo_odd_data_count ),
132-
.empty (fifo_odd_data_out_not_valid) //equivalent to not data_out_valid
130+
.empty (fifo_odd_data_out_not_valid)
133131
);
134-
//conclusion fifo odd instatiation convert negated not_ready/not_valid signals to "standard" ready/valid interface.
135132
assign fifo_odd_data_in_ready = ~ fifo_odd_data_in_not_ready ;
136133
assign fifo_odd_data_out_valid = ~ fifo_odd_data_out_not_valid;
137134

138-
//select fifo current and fifo next according to cur_is_even_character signal
139135
always_comb begin : selector_fifo_current_fifo_next
140136

141137
if ( cur_is_even_character == 1'b1 )
142-
begin //even is current and odd is next_char
138+
begin
143139
fifo_cur_char_data_in_ready = fifo_even_data_in_ready ;
144140
fifo_even_data_in = fifo_cur_char_data_in ;
145141
fifo_even_data_in_valid = fifo_cur_char_data_in_valid ;
@@ -157,7 +153,7 @@ module basic_block #(
157153
fifo_next_char_data_count = fifo_odd_data_count ;
158154
end
159155
else
160-
begin //odd is current and even is next_char
156+
begin
161157
fifo_cur_char_data_in_ready = fifo_odd_data_in_ready ;
162158
fifo_odd_data_in = fifo_cur_char_data_in ;
163159
fifo_odd_data_in_valid = fifo_cur_char_data_in_valid ;
@@ -176,18 +172,14 @@ module basic_block #(
176172
end
177173
end
178174

179-
// make so that content of fifo_next_char is not consumed.
175+
180176
assign fifo_next_char_data_out_ready = 1'b0;
181177

182-
//output_pc is redirected toward output after having concatenated with output_pc_is_directed_to_current
183178
assign output_pc_and_current = {output_pc, output_pc_is_directed_to_current};
184-
//input_pc_and_current is splitted in input_pc and input_pc_is_directed_to_current
179+
185180
assign input_pc_is_directed_to_current = input_pc_and_current[0];
186181
assign input_pc = input_pc_and_current[1+:PC_WIDTH] ;
187182

188-
//demux to drive input_pc_and_current toward correct fifo.
189-
//to avoid a combinational loop (switches can decide to move data toward one or the other output port depending on output ready, but in principle output ready depends also on targeted fifo which is specified in data).
190-
//conservative(certain instruction which in principle could have been stored are refused) but correct
191183
assign input_pc_ready = fifo_cur_char_data_in_ready && fifo_next_char_data_in_ready;
192184
always_comb begin : demux_for_pc_in
193185
fifo_cur_char_data_in = { PC_WIDTH{1'b0} };
@@ -196,25 +188,21 @@ module basic_block #(
196188
if(input_pc_is_directed_to_current)
197189
begin
198190
fifo_cur_char_data_in = input_pc ;
199-
fifo_cur_char_data_in_valid = input_pc_valid && input_pc_ready; //since for outside bb input is ready if both fifo_cur_char and fifo_next_char are ready, their valid has to take into account that to avoid that fifo_latches it
191+
fifo_cur_char_data_in_valid = input_pc_valid && input_pc_ready;
200192

201193
fifo_next_char_data_in_valid= 1'b0;
202194
end
203195
else
204196
begin
205197
fifo_next_char_data_in = input_pc ;
206-
fifo_next_char_data_in_valid = input_pc_valid && input_pc_ready; //since for outside bb input is ready if both fifo_cur_char and fifo_next_char are ready, their valid has to take into account that to avoid that fifo_latches it
198+
fifo_next_char_data_in_valid = input_pc_valid && input_pc_ready;
207199

208200
fifo_cur_char_data_in_valid = 1'b0;
209201
end
210202
end
211203

212-
//compute the approximate latency seen outside thought of max between odd and even but lead to high fanout-> setup violation
213-
//opted for a simpler computation: consider only fifo_cur_char length.
214-
//always_comb begin : latency_computation
215-
// if( fifo_odd_data_count > fifo_even_data_count) input_pc_latency = fifo_odd_data_count + 1;
216-
// else input_pc_latency = fifo_even_data_count + 1;
217-
//end
204+
205+
218206
if( CONSIDER_PIPELINE_FIFO == 1)
219207
begin
220208
always_comb
@@ -233,104 +221,63 @@ module basic_block #(
233221
end
234222

235223

236-
//running if regex_cpu has taken some instruction and hence the data_out_ready=0
237-
// or some instructions are saved in curr character fifo and hence fifo_cur_char_data_out_valid=1
224+
238225
always_comb begin : running_definition
239226
running = fifo_cur_char_data_out_valid || regex_cpu_running;
240227
end
241228

242229

243-
/////////////////////////////////////////////////////////////////////////////
244-
// Computing part of the basic block
245-
/////////////////////////////////////////////////////////////////////////////
246-
// go signal enable dequeue process from fifo_cur_char and plays the role of an enabler regex_cpu
230+
247231
assign fifo_cur_char_data_out_ready = go && regex_cpu_input_pc_ready ;
248232
assign regex_cpu_input_pc_valid = go && fifo_cur_char_data_out_valid;
249-
if(PIPELINED)
250-
begin : g
233+
251234

252-
regex_cpu_pipelined #(
253-
.PC_WIDTH (PC_WIDTH ),
254-
.CHARACTER_WIDTH (CHARACTER_WIDTH ),
255-
.MEMORY_WIDTH (I_WIDTH ),
256-
.MEMORY_ADDR_WIDTH (CPU_MEMORY_ADDR_WIDTH ),
257-
.FIFO_WIDTH_POWER_OF_2 (REGEX_CPU_FIFO_WIDTH_POWER_OF_2 )
258-
) aregex_cpu (
259-
.clk (clk ),
260-
.reset (reset ),
261-
.current_character (current_character ),
262-
.input_pc_ready (regex_cpu_input_pc_ready ),
263-
.input_pc (fifo_cur_char_data_out ),
264-
.input_pc_valid (regex_cpu_input_pc_valid ),
265-
.memory_ready (regex_cpu_memory_ready ),
266-
.memory_addr (regex_cpu_memory_addr ),
267-
.memory_data (regex_cpu_memory_data ),
268-
.memory_valid (regex_cpu_memory_valid ),
269-
.output_pc_is_directed_to_current (output_pc_is_directed_to_current ),
270-
.output_pc_ready (output_pc_ready ),
271-
.output_pc (output_pc ),
272-
.output_pc_valid (output_pc_valid ),
273-
.accepts (accepts ),
274-
.running (regex_cpu_running ),
275-
.latency (regex_cpu_latency )
276-
);
277-
end
278-
else
279-
begin : g
280-
regex_cpu #(
281-
.PC_WIDTH (PC_WIDTH ),
282-
.CHARACTER_WIDTH (CHARACTER_WIDTH ),
283-
.MEMORY_WIDTH (I_WIDTH ),
284-
.MEMORY_ADDR_WIDTH (CPU_MEMORY_ADDR_WIDTH )
285-
) aregex_cpu (
286-
.clk (clk ),
287-
.reset (reset ),
288-
.current_character (current_character ),
289-
.input_pc_ready (regex_cpu_input_pc_ready ),
290-
.input_pc (fifo_cur_char_data_out ),
291-
.input_pc_valid (regex_cpu_input_pc_valid ),
292-
.memory_ready (regex_cpu_memory_ready ),
293-
.memory_addr (regex_cpu_memory_addr ),
294-
.memory_data (regex_cpu_memory_data ),
295-
.memory_valid (regex_cpu_memory_valid ),
296-
.output_pc_is_directed_to_current (output_pc_is_directed_to_current ),
297-
.output_pc_ready (output_pc_ready ),
298-
.output_pc (output_pc ),
299-
.output_pc_valid (output_pc_valid ),
300-
.accepts (accepts )
301-
);
302-
assign regex_cpu_latency = 0;
303-
assign regex_cpu_running = ~fifo_cur_char_data_out_ready ;
304-
end
235+
regex_cpu_pipelined #(
236+
.PC_WIDTH (PC_WIDTH ),
237+
.CHARACTER_WIDTH (CHARACTER_WIDTH ),
238+
.MEMORY_WIDTH (I_WIDTH ),
239+
.MEMORY_ADDR_WIDTH (CPU_MEMORY_ADDR_WIDTH ),
240+
.FIFO_WIDTH_POWER_OF_2 (REGEX_CPU_FIFO_WIDTH_POWER_OF_2 )
241+
) aregex_cpu (
242+
.clk (clk ),
243+
.reset (reset ),
244+
.current_character (current_character ),
245+
.input_pc_ready (regex_cpu_input_pc_ready ),
246+
.input_pc (fifo_cur_char_data_out ),
247+
.input_pc_valid (regex_cpu_input_pc_valid ),
248+
.memory_ready (regex_cpu_memory_ready ),
249+
.memory_addr (regex_cpu_memory_addr ),
250+
.memory_data (regex_cpu_memory_data ),
251+
.memory_valid (regex_cpu_memory_valid ),
252+
.output_pc_is_directed_to_current (output_pc_is_directed_to_current ),
253+
.output_pc_ready (output_pc_ready ),
254+
.output_pc (output_pc ),
255+
.output_pc_valid (output_pc_valid ),
256+
.accepts (accepts ),
257+
.running (regex_cpu_running ),
258+
.latency (regex_cpu_latency )
259+
);
260+
261+
262+
263+
cache_block_directly_mapped #(
264+
.DWIDTH (I_WIDTH ),
265+
.CACHE_WIDTH_BITS (CACHE_WIDTH_BITS ),
266+
.BLOCK_WIDTH_BITS (CACHE_BLOCK_WIDTH_BITS ),
267+
.ADDR_IN_WIDTH (CPU_MEMORY_ADDR_WIDTH )
268+
) a_cache (
269+
.clk (clk ),
270+
.reset (reset ),
271+
.addr_in_valid (regex_cpu_memory_valid ),
272+
.addr_in (regex_cpu_memory_addr ),
273+
.addr_in_ready (regex_cpu_memory_ready ),
274+
.data_out (regex_cpu_memory_data ),
275+
.addr_out_valid (memory_valid ),
276+
.addr_out (memory_addr ),
277+
.addr_out_ready (memory_ready ),
278+
.data_in (memory_data )
279+
);
305280

306-
//depending on CACHE_WIDTH_BITS
307-
if (CACHE_WIDTH_BITS <= 0)
308-
begin
309-
assign memory_addr = regex_cpu_memory_addr ;
310-
assign memory_valid = regex_cpu_memory_valid;
311-
assign regex_cpu_memory_ready = memory_ready ;
312-
assign regex_cpu_memory_data = memory_data ;
313-
end
314-
else
315-
begin
316-
cache_block_directly_mapped #(
317-
.DWIDTH (I_WIDTH ),
318-
.CACHE_WIDTH_BITS (CACHE_WIDTH_BITS ),
319-
.BLOCK_WIDTH_BITS (CACHE_BLOCK_WIDTH_BITS ),
320-
.ADDR_IN_WIDTH (CPU_MEMORY_ADDR_WIDTH )
321-
) a_cache (
322-
.clk (clk ),
323-
.reset (reset ),
324-
.addr_in_valid (regex_cpu_memory_valid ),
325-
.addr_in (regex_cpu_memory_addr ),
326-
.addr_in_ready (regex_cpu_memory_ready ),
327-
.data_out (regex_cpu_memory_data ),
328-
.addr_out_valid (memory_valid ),
329-
.addr_out (memory_addr ),
330-
.addr_out_ready (memory_ready ),
331-
.data_in (memory_data )
332-
);
333-
end
334281

335282

336283
endmodule

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