Basic building block of the digital circuit is written in verilog like half adder. full adder, multiplexer,flipflops of various configurations, and other synchrounous circuits
Intermideatte level projects like FIFO (First-In-First-Out), UART (Universal Asynchronous Receiver Transmitter), I2C (Inter Integrated Communication Protocol), SPI (Serial Peripheral Interface), Ethernet and AXI Interconnects will be added in the upcoming future.
Various modules are simulated in the Xilinx vivado tool, Modelsim, Icarus Verilog, EDA Playground and hdl bits.com
The waveforms results are furthermore attachedwith each project for reference.