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1. RISC-V-CPU RISC-V-CPU Public

   RISC-V CPU: Single-Cycle Processor for RISC-V ISA Built in Verilog - SUSTech's project of course CS202: Computer Organization in Spring 2024 - Score: 104.5/100

   VHDL 1 1

2. xv6-signal-handling xv6-signal-handling Public

   xv6-signal-handling: POSIX-style signal implementation for xv6 kernel - SUSTech project of CS302: Operating Systems in Spring 2025 - Score: 100/100

   Python

3. Digital-Piano Digital-Piano Public

   Digital Piano: FPGA project in Verilog based on Xilinx Atrix-7 EGO1 - SUSTech's project of course CS207: Digital Logic in Fall 2023 - Score: 120/100

   Verilog 7 1

4. KG-Based-Recommender-System KG-Based-Recommender-System Public

   Knowledge Graph-Based Recommender System (KGRS) - SUSTech project of CS303: Artificial Intelligence in Fall 2024 - Score: 15/15

   Python 1

5. LLM-Detective LLM-Detective Public

   LLM Detective: A Comparative Study of Supervised and Zero-Shot Methods for Detecting Texts Generated by Large Language Models - SUSTech project of CS310: Natural Language Processing in Spring 2025

   Python 2

6. Jungle-Chess Jungle-Chess Public

   Jungle: Chess Game Engine - Implementation of Minimax, Alpha-Beta Pruning, Move Ordering, and Quiescence Search - SUSTech project of course CS109: Introduction to Programming in Spring 2023 - Score…

   Java 5