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1.8.0
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@shtaxxx shtaxxx released this 19 Nov 11:17
· 607 commits to master since this release
1.8.0
1699094

Update

  • veriloggen.core: N-dimension array is supported for almost variable types.
  • veriloggen.stream: Accumulator registers in stream pipelines are kept after executions for continuous sequent executions.
  • veriloggen.types.axi: The bit-width of AxLOCK is changed to 1 according to the AXI4 specification.

Test environment

macOS 10.15.1

  • Python 3.7.5
  • Icarus Verilog 10.3
  • Pyverilog 1.2.0

Ubuntu 18.04.3

  • Python 3.6.8
  • Icarus Verilog 10.1
  • Pyverilog 1.2.0
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