OpenLane-VSD : DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING

Author: Soham Das

Introduction

OpenLane is an ASIC infrastructure library based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, KLayout and a number of custom scripts for design exploration and optimization.

A reference flow, "Classic", performs all ASIC implementation steps from RTL all the way down to GDSII. A Process Design Kit (PDK) is a set of files used within the semiconductor industry to model a fabrication process for the design tools used to design an integrated circuit. Here we are using:

The Google SkyWater 130 PDK is an open-source toolkit for designing computer chips at the 130nm scale. Developed by Google and SkyWater Technology, it makes chip design accessible to everyone, from students to researchers, and supports innovation by providing essential design resources and compatibility with various design tools.

Follow the official OpenLane Documentation to get started. You can discuss OpenLane 2 in the #openlane-2 channel of the Efabless Open Source Silicon Slack.

Openlane flow

Overview of Physical Design flow

Place and Route (PnR) is the core of any ASIC implementation and Openlane flow integrates into it several key open source tools which perform each of the respective stages of PnR. Below are the stages and the respective tools (in ( )) that are called by openlane for the functionalities as described:

• Synthesis

  • Generating gate-level netlist (yosys).
  • Performing cell mapping (abc).
  • Performing pre-layout STA (OpenSTA).

• Floorplanning

  • Defining the core area for the macro as well as the cell sites and the tracks (init_fp).
  • Placing the macro input and output ports (ioPlacer).
  • Generating the power distribution network (pdn).

• Placement

  • Performing global placement (RePlAce).
  • Performing detailed placement to legalize the globally placed components (OpenDP).

• Clock Tree Synthesis (CTS)

  • Synthesizing the clock tree (TritonCTS).

• Routing

  • Performing global routing to generate a guide file for the detailed router (FastRoute).
  • Performing detailed routing (TritonRoute).

• GDSII Generation

  • Streaming out the final GDSII layout file from the routed DEF (Magic).

Try it out!

You can try OpenLane right in your browser, free-of-charge, using Google Colaboratory by following this link.

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Motive

We will use the PicoRV32 — a small and stable RISC-V core — as our RTL design for this backend flow.
Additionally, we will create a standard cell library that will be used to generate the netlist from the RTL code. We will analyze critical aspects of the design, such as hold time, setup time, and more.

OpenLane Setup

OpenLane is successfully run.

Tech File Exploration

Now we will delve into some of the deafult configurations which skywater130nm pdk provides. For example, below are the default settings found in the openlane configurations.

Here are the defaults for floorplan found in floorplan.tcl file

Finding Flop ratio

The general rule of thumb is: dff_count / total_number_of_cells
We have done it for our case here:

At the very end the chip area is also observed:

Looking into Routing and Placement

The first step is to bind the netlist with physical cells i.e. cells with real dimension. These blocks are sourced from a "shelf", known as a library.The library has cells with various shapes, dimensions and also contains information about the delay information. The library contains various sizes of cells with the same functionality too - since bigger cells have lesser resistance.

The second step is PLACEMENT, which is done based on connectivity. As can be seen, flip flop 1 is close to the Din1 pin and flip flop 2 is close to Dout1 pin. Combinational cells are placed in close proximity to FF1 and FF2 as to reduce delay.

Viewing the floorplan and placement

In the terminal, the below command is run to see the floorplan in Magic vlsi. Note that the placement is yet to be done.

magic -T /Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.floorplan.def &

Below is the png image of the core after floorplan is done.

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Below is the post-placement png image:

Below is the image of the same in Magic VLSI.

Typical Characterization Flow

The standard cell characterization process involves the following steps:

1. Reading SPICE model files containing device-level parameters.
2. Importing the netlist extracted from SPICE simulations.
3. Identifying buffer behavior to understand drive strength and signal propagation.
4. Parsing subcircuits defined in the SPICE hierarchy.
5. Connecting required power supplies (VDD and GND) to the circuit.
6. Applying input stimulus to simulate switching activity.
7. Adding appropriate output load capacitance to mimic real usage conditions.
8. Defining simulation control commands (e.g., transient or DC analysis).

The flow is typically driven by a configuration file fed into a characterization tool such as GUNA. The tool performs simulations and generates timing, power, and noise models, outputting them in .lib (Liberty) format.

Installing Inverter layout

Here we are majorly focused on the inverter simulations. We alredy have the inverter ready. The repo is cloned into our system through this link in the below mentioned directory

/home/vsduser/Desktop/work/tools/openlane_working_dir/openlane

Commands given:

git clone https://github.com/nickson-jose/vsdstdcelldesign.git

Here we have the mag file of the inverter ready.

Now the final inverter layout is observed.

Ngspice Simulations

It is to be noted that ngspice was needed to be installed in the specified directory.

~/Desktop/work/tools/openlane_working_dir/openlane/vsdstdcelldesign

Command in terminal:

sudo apt install ngspice

sky130_inv.spice file was modified as below:

Simulation setup is done and well running.


Now we can plot various graphs.

Upon running command in ngspice:

plot y vs time a

The below graph is obtained and is the required transient response of an inverter.

Looking into parameters

Here we will consider the below circuit of an inverter:

Rise transition: time taken by output wave to transit from a value of 20% of its max value to 80% of max value.

Fall transition: time taken by output wave to transit from a value of 80% of its max value to 20% of max value.

Fall Cell Delay: difference between time period when input has fallen to its 50% and output has risen to its 50%.

Rise Cell Delay: difference between time period when output has fallen to its 50% and input has risen to its 50%.

Rise time obtained by the difference:

The 16 Mask Process

#	Mask Name	Purpose
1	Active (Active Area or Diffusion)	Defines where diffusion (source/drain) can occur.
2	N-Well	Defines n-well areas for PMOS transistors.
3	P-Well	Defines p-well areas for NMOS transistors (in twin-tub process).
4	Field Oxide (LOCOS/Isolation)	Isolation regions via field oxide or STI.
5	Threshold Adjustment (VT)	For selective threshold voltage implantations.
6	Channel Stop	Prevents leakage by doping field regions.
7	Poly (Gate)	Defines polysilicon gates of transistors.
8	Lightly Doped Drain (LDD) N+	Forms lightly doped n-type extension for NMOS.
9	Lightly Doped Drain (LDD) P+	Forms lightly doped p-type extension for PMOS.
10	Spacer Etch (Sidewall Spacers)	Defines oxide spacers for self-alignment.
11	Source/Drain N+	Heavily doped n-type source/drain (NMOS).
12	Source/Drain P+	Heavily doped p-type source/drain (PMOS).
13	Contact	Defines contact holes between metal and active regions.
14	Metal1	First layer of metal interconnect.
15	Via1	Connects Metal1 to Metal2.
16	Metal2	Second layer of metal interconnect.

Lab Introduction to Magic Tool Options and DRC Rules by Tim Edward

Link to Google_Skywaters Design Rules: - https://skywater-pdk.readthedocs.io/en/main/rules/periphery.html

For reference , we can use the github repo of Google-Skywater: - https://github.com/google/skywater-pdk

One can read here also : - https://opencircuitdesign.com/magic Specefically section 2,6 of magic tutrial was mentioned.

for the lab we need to download the lab files, which can be done through this command -: wget http://opencircuitdesign.com/open_pdks/archive/drc_tests.tgz

Steps to configure OpenSTA for Post-synthesis Timing Analysis

We will give the following commmands in the terminal in openlane directory

prep -design picorv32a -tag 01-04_12-54 -overwrite

set lefs [glob $::env(DESIGN_DIR)/src/*.lef]

add_lefs -src $lefs

echo $::env(SYNTH_STRATEGY)

set ::env(SYNTH_STRATEGY) "DELAY 3"

echo $::env(SYNTH_BUFFERING)

echo $::env(SYNTH_SIZING)

set ::env(SYNTH_SIZING) 1

echo $::env(SYNTH_DRIVING_CELL)

run_synthesis  

prep -design picorv32a -tag 01-04_12-54 -overwrite 

is used to overwrite the existing files with previous values of simulations. After synthesis, we have observed that the slack is negative.

Now run_synthesis we will see chip area has incresed and the value of slack has reduced. Since synthesis of the picorv32a is successful, so we will run the floorplan using command run_floorplan

Since, we are getting the error so first again we have to do the synthesis using the commands mentioned earlier and then we will use following commands to do the floorplan,

init_floorplan

place_io

tap_decap_or 

now we are good to run_placement.

Here placement is succesfull now without any error.

Lab steps to Optimize synthesis to reduce setup violations

Now we will change the FANOUT parameter and again do the synthesis,

 prep -design picorv32a -tag 02-04_05-27 -overwrite

set lefs [glob $::env(DESIGN_DIR)/src/*.lef]

add_lefs -src $lefs

set ::env(SYNTH_SIZING) 1

set ::env(SYNTH_MAX_FANOUT) 4

echo $::env(SYNTH_DRIVING_CELL)

run_synthesis 

Clock Tree Routing and Buffering Using H-Tree Algorithm

Clock tree synthesis:- Let's connect clk1 to FF1 & FF2 of stage 1 and FF1 of stage 3 and FF2 of stage 4 with physical wire.

Now let's see what is the problem with this? Let's consider some physical distance from clk to FF1 and FF2 , so due to this t2>t1.

Skew= t2-t1, and skew should be 0ps

Previously we have build bad tree now we will try to modify that in a smarter way. Hrre clk will come in somewhere mid points with this clk will reach to every flip flop at almost same time. In the same way we will connect the clk2 with flip flops like midpoint manner.

Now will se clock tree synthesis(Buffering), Let's we have some clock route through which it has to reach to particular locations and clock end points and in the path many capacitance, resitors are there.

Because of the wire length we did not get the same wave form at ouput as input and bcz of RC networks , so to resolve this problem we use repeaters. The only difference between the repeaters we use for clock or for data path is that clock repeaters repeaters will have equal rise and fall time.

Clock Net Shielding:- Till now we have built the clk tree in such a fashion that the skew between the launch flop and capture flop is 0. Skew means the latency difference between clk ports of the flop pins. Clk net shielding is the critical net scene in the design. We take the particular clk net and shield it means we protect the clk from the outside world, it's like house for tha clk.

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Routing and design rule check (DRC): Intro to Maze routing using Lee's Algorithm

Maze-Routing(Lee's Algorithm):- Therse should not be zig-zag lines of connections most of the connections should be in L shape or in Z shape. So according to algorithm first it create some grids and grids are routing at the backend. It's called as routing grid. There are some numbers of grids on this routig having some dimensions. SO here we are having two points one is 'Source' and the other is 'Target'. With the help of this routing grid algorithm has to find out the best possible way between them.

First step is algorithm tries to lable all of the grids surrounded. Only the adjacent horizontal and vertical grids are labeled not the digonal one as shown in the image below.

SO now there are so many ways to reach to target from source but we have to choose the best shortest possible way to reach the target.And we need to avoid the zig-zag way better to choose 'L' shape routing'.

Design Rule Check

Rule 1) Wire width:- Width of the wire should be minimum that derived from the optical wavelenth of lithography technique applied.

Rule 2) Wire Pitch:- The minimum pitch between two wire should be this much as shown in the figure below.

Rule 3) Wire Spacing:- The wire spacing between two wires should be as shown in the image below.

Now let's take the below circuit for example:

Solution of this signal short problem is take one of the wire and put it on the other metal layer. usually upper metal is wider than the lower metal.

Rule 1) Via Width:- via width should be some minimum value.
Rule 2) Via Spacing:- Via spacing should be minimum value.

After routing and DRC the next step is Parasitic extraction. Resistance and capacitance present on every wire should be extracted and use for further process.

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Power Distribution Network and Routing

It is shown below how standard cells are powered up :- power/ground pads -> power/ground ring-> power/ground straps -> power/ground rails

Here green color is representing the chip, and yellow, red and blue boxes are the I/O pins,power and ground pads respectively. Power is transfered to the rings from the pads through the black dots shown in the image on the cross section points of the ring and pads. We have vertical and horizontal tracks which ensures that the power is being transfered from the ring to chip this is shown by the red and blue color. This is how power planing works in physical design of any device.

The total process of routing is devided into two part.

1. Fast route (Global route) |
2. Detailed Route

In the Global route, the routing region is devided into the rectangular grids cells as shown in the figure above. And it is represented as cores 3D routing graph. Global route is done by FAST route engine.The detailed route is done by TritonRoute engine.

The algorithm requires the determination of the cost associated with each APC and the calculation of the minimum spanning tree between the APCs to find the optimal points between two APCs. The next step involves post-routing STA analysis, which requires the extraction of parasitic effects (SPEF). Since OpenLANE does not have a SPEF extraction tool, this process needs to be done outside of OpenLANE.

Final Stage

The last stage will be to extract the GDSII file ready for fabrication. This uses Magic to stream the GDSII file runs/02-06_13-52/results/magic/picorv32a.gds. This GDSII file can then be read by Magic. The last stage is to extract the GDSII file ready for fabrication through run_magic.

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Conclusion

This documentation serves as a comprehensive walkthrough of the digital ASIC design backend flow using open-source tools and the Sky130 PDK. From RTL to GDSII, each stage has been detailed with supporting visuals, real tool outputs, and practical insights.

Key Takeaways

• Understanding of open-source RTL and EDA tools like Yosys, OpenROAD, and Magic.
• Hands-on application of the OpenLane flow for physical design automation.
• Deep insights into timing analysis, power planning, antenna effects, and routing challenges.
• Exposure to the SkyWater 130nm process and characterization fundamentals.

References

Special thanks to VSD, OpenLane, SkyWater, and the entire open-source hardware community for enabling such accessible learning platforms.

https://www.vlsisystemdesign.com/digital-vlsi-soc-design-and-planning/

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