Add signed/fixedpoint properties

[darsor]

Description of change

Add support for the is_signed, intwidth, and fracwidth properties as discussed in SystemRDL/#188.

For a full description of the new features, see the updated documentation included in the PR.

Checklist

• I have reviewed this project's contribution guidelines
• This change has been tested and does not break any of the existing unit tests. (if unable to run the tests, let us know)
• If this change adds new features, I have added new unit tests that cover them.

[amykyta3]

This is freaking awesome. Thanks for doing this!
I left a handful of comments. Mostly cleanup and simplifications

[amykyta3]

Also, since I assume you're mirroring this change in VHDL, you'll want to match the version. This will end up being released under regblock v1.1.0

[darsor]

Thanks for the feedback! I've implemented all your suggestions. I also fleshed out the docs a bit and added some examples.

I can squash all these commits if you'd like, or I assume Github can squash them automatically when merging.

[amykyta3]

Looks good!
Thanks again for doing this, and being such a good PR submitter. Its rare that I get such a high quality PR.