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Verilog emission refactor #392

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Verilog emission refactor

Verilog emission refactor #392

Triggered via pull request April 15, 2025 22:23
@matth2kmatth2k
synchronize #133
asic-verilog
Status Failure
Total duration 2m 18s
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rust.yml

on: pull_request
cargo test
21s
cargo test
cargo fmt
13s
cargo fmt
clippy_check
1m 5s
clippy_check
Integration Tests
2m 8s
Integration Tests
Test Speed
1m 32s
Test Speed
Code Coverage
50s
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cargo test
Process completed with exit code 101.
Code Coverage
Process completed with exit code 1.
Test Speed
Process completed with exit code 1.
Integration Tests
Process completed with exit code 1.