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Verilog emission refactor #393

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Verilog emission refactor

Verilog emission refactor #393

Triggered via pull request April 15, 2025 22:33
@matth2kmatth2k
synchronize #133
asic-verilog
Status Failure
Total duration 2m 27s
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rust.yml

on: pull_request
cargo test
24s
cargo test
cargo fmt
8s
cargo fmt
clippy_check
1m 3s
clippy_check
Integration Tests
2m 16s
Integration Tests
Test Speed
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Code Coverage
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Code Coverage
Process completed with exit code 1.
clippy_check
Process completed with exit code 101.
Integration Tests
Process completed with exit code 1.