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Finish Verilog backend unification (#137) #422

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Finish Verilog backend unification (#137)

Finish Verilog backend unification (#137) #422

Triggered via push April 21, 2025 18:58
@matth2kmatth2k
pushed 27ec13a
main
Status Success
Total duration 2m 53s
Artifacts –

rust.yml

on: push
cargo test
38s
cargo test
cargo fmt
9s
cargo fmt
clippy_check
1m 9s
clippy_check
Integration Tests
2m 41s
Integration Tests
Test Speed
1m 50s
Test Speed
Code Coverage
39s
Code Coverage
Markdown format
38s
Markdown format
Python format
9s
Python format
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