Implement rest of PrimitiveTypes as rewrite rules (#141)

Author: matth2k

src/asic.rs

@@ -297,8 +297,20 @@ pub fn asic_rewrites() -> Vec<egg::Rewrite<CellLang, CellAnalysis>> {
     rules
         .push(rewrite!("xor2_x1"; "(OR (AND ?b (INV ?a)) (AND ?a (INV ?b)))" => "(XOR2_X1 ?a ?b)"));
     rules.push(rewrite!("inv_x1"; "(INV ?a)" => "(INV_X1 ?a)"));
-    rules.push(rewrite!("aoi_x1"; "(INV (OR (AND ?a ?b) ?c))" => "(AOI21_X1 ?a ?b ?c)"));
-    rules.push(rewrite!("oai_x1"; "(INV (AND (OR ?a ?b) ?c))" => "(OAI21_X1 ?a ?b ?c)"));
+    rules.push(rewrite!("aoi21_x1"; "(INV (OR (AND ?b ?c) ?a))" => "(AOI21_X1 ?a ?b ?c)"));
+    rules.push(rewrite!("oai21_x1"; "(INV (AND (OR ?b ?c) ?a))" => "(OAI21_X1 ?a ?b ?c)"));
+    rules.push(
+        rewrite!("aoi22_x1"; "(INV (OR (AND ?c ?d) (AND ?a ?b)))" => "(AOI22_X1 ?a ?b ?c ?d)"),
+    );
+    rules.push(
+        rewrite!("oai22_x1"; "(INV (AND (OR ?c ?d) (OR ?a ?b)))" => "(OAI22_X1 ?a ?b ?c ?d)"),
+    );
+    rules.push(
+        rewrite!("aoi211_x1"; "(INV (OR ?b (OR (AND ?c ?d) ?a)))" => "(AOI211_X1 ?a ?b ?c ?d)"),
+    );
+    rules.push(
+        rewrite!("oai211_x1"; "(INV (AND ?b (AND (OR ?c ?d) ?a)))" => "(OAI211_X1 ?a ?b ?c ?d)"),
+    );
 
     rules
 }

src/bin/emit-verilog.rs

@@ -5,7 +5,7 @@ use std::{
 
 use clap::Parser;
 use egg::RecExpr;
-use lut_synth::{driver::Canonical, lut::LutLang, verilog::SVModule};
+use lut_synth::{asic::CellLang, driver::Canonical, lut::LutLang, verilog::SVModule};
 /// Emit a LutLang Expression as a Verilog Netlist
 #[derive(Parser, Debug)]
 #[command(version, about, long_about = None)]
@@ -28,6 +28,10 @@ struct Args {
     /// Canonicalize the input expression
     #[arg(short = 'c', long, default_value_t = false)]
     canonicalize: bool,
+
+    /// Parse input as a CellLang expression
+    #[arg(short = 'a', long, default_value_t = false)]
+    asic: bool,
 }
 
 fn main() -> std::io::Result<()> {
@@ -67,18 +71,27 @@ fn main() -> std::io::Result<()> {
             continue;
         }
         let expr = line.split("//").next().unwrap();
-        let expr: RecExpr<LutLang> = expr
-            .parse()
-            .map_err(|s| std::io::Error::new(std::io::ErrorKind::Other, s))?;
+        let module = if !args.asic {
+            let expr: RecExpr<LutLang> = expr
+                .parse()
+                .map_err(|s| std::io::Error::new(std::io::ErrorKind::Other, s))?;
+
+            let expr = if args.canonicalize {
+                LutLang::canonicalize_expr(expr)
+            } else {
+                expr
+            };
 
-        let expr = if args.canonicalize {
-            LutLang::canonicalize_expr(expr)
+            SVModule::from_luts(expr, mod_name.clone(), args.output_names.clone())
+                .map_err(|s| std::io::Error::new(std::io::ErrorKind::Other, s))?
         } else {
-            expr
-        };
+            let expr: RecExpr<CellLang> = expr
+                .parse()
+                .map_err(|s| std::io::Error::new(std::io::ErrorKind::Other, s))?;
 
-        let module = SVModule::from_luts(expr, mod_name.clone(), args.output_names.clone())
-            .map_err(|s| std::io::Error::new(std::io::ErrorKind::Other, s))?;
+            SVModule::from_cells(expr, mod_name.clone(), args.output_names.clone())
+                .map_err(|s| std::io::Error::new(std::io::ErrorKind::Other, s))?
+        };
         print!("{}", module);
         break;
     }

src/verilog.rs

@@ -802,7 +802,7 @@ impl VerilogEmission for CellLang {
                 let inputs = self.children();
                 let gate_type = self
                     .get_gate_type()
-                    .expect("CellLang gates should have a primitive type");
+                    .ok_or("CellLang gates should have a primitive type".to_string())?;
                 let port_list = gate_type.get_input_list();
                 // TODO(matth2k): Carry through drive strength
                 let mut prim =
@@ -882,7 +882,7 @@ impl VerilogEmission for LutLang {
                 let inputs = self.children();
                 let gate_type = self
                     .get_gate_type()
-                    .expect("CellLang gates should have a primitive type");
+                    .ok_or("LutLang gates should have a primitive type".to_string())?;
                 let port_list = gate_type.get_input_list();
                 let mut prim = SVPrimitive::new_gate(gate_type.clone(), fresh_prim_name());
                 for (input, port) in inputs.iter().zip(port_list) {

tests/asic/cla.txt

@@ -2,4 +2,4 @@
 
 // 2-bit CLA
 (OR (OR (AND a1 b1) (AND (AND a0 b0) (OR a1 b1))) (AND c0 (AND (OR a1 b1) (OR a0 b0))))
-// CHECK: (NAND2_X1 (NAND2_X1 a1 b1) (OAI21_X1 a1 b1 (NAND2_X1 (NAND2_X1 a0 b0) (OAI21_X1 a0 b0 c0))))
+// CHECK: (NAND2_X1 (NAND2_X1 a1 b1) (OAI21_X1 (NAND2_X1 (NAND2_X1 a0 b0) (OAI21_X1 c0 a0 b0)) a1 b1))

tests/asic/cla.v

@@ -82,9 +82,9 @@ module cla (
   // CHECK: );
   // CHECK: OAI21_X1 #(
   // CHECK: ) __6__ (
-  // CHECK:     .A(a0),
-  // CHECK:     .B1(b0),
-  // CHECK:     .B2(c0),
+  // CHECK:     .A(c0),
+  // CHECK:     .B1(a0),
+  // CHECK:     .B2(b0),
   // CHECK:     .ZN(__1__)
   // CHECK: );
   // CHECK: NAND2_X1 #(
@@ -95,9 +95,9 @@ module cla (
   // CHECK: );
   // CHECK: OAI21_X1 #(
   // CHECK: ) __8__ (
-  // CHECK:     .A(a1),
-  // CHECK:     .B1(b1),
-  // CHECK:     .B2(__2__),
+  // CHECK:     .A(__2__),
+  // CHECK:     .B1(a1),
+  // CHECK:     .B2(b1),
   // CHECK:     .ZN(__3__)
   // CHECK: );
   // CHECK: NAND2_X1 #(