v0.5.1 Bug Fixes

What's Changed

• Add parameter for decompose in any order by @matth2k in #100
• Add append.py script by @matth2k in #101
• Support GND primitive by @matth2k in #102
• Support Verilog instances with constant inputs by @arnavm30 in #103
• Propagate literal parsing errors by @matth2k in #104
• Allow 'Don't Care' to be parsed into LutLang by @matth2k in #105
• Speed up cycle detection by @matth2k in #108
• Bump version by @matth2k in #109

Full Changelog: v0.5.0...v0.5.1

v0.5.0

What's Changed

• Add disassemble extraction strategy by @matth2k in #83
• Add disassembly test by @matth2k in #84
• Add --verbose option to parse-verilog by @matth2k in #86
• Fix outputs driven directly by an input by @matth2k in #87
• Don't add outputs directly to signals list by @matth2k in #89
• Fix Verilog when multiple outputs assign to the same net by @matth2k in #90
• Add reconfigurable disassemble extraction strategy by @matth2k in #91
• Don't need to clone the SynthRequest by @matth2k in #93
• Follow Verilog rule for escape identifiers by @matth2k in #94
• Remove command option for fam, update docs by @matth2k in #95
• Added lvv-vivado by @berkgokmen14 in #96
• Support MUXF7 by @matth2k in #97
• Move mux expansion rule by @matth2k in #98
• Add driver script for re-synthesis feature by @matth2k in #99

Full Changelog: v0.3.2...v0.5.0

v0.3.2

What's Changed

• Add gate info to report by @matth2k in #80
• Track cut information in analysis by @matth2k in #77
• Implement dynamic decompositions by @matth2k in #82

Full Changelog: v0.3.0...v0.3.2

v0.3.0

Included are x86 gnu linux binaries.

What's Changed

• Handle arbitrary assignments in Verilog by @matth2k in #62
• Add register count to report by @matth2k in #63
• fix shebangs by @arnavm30 in #65
• Add cat.py to tool path by @matth2k in #66
• Add stop reason to report by @matth2k in #68
• Add ILP extractor by @matth2k in #70
• Fix file perms by @matth2k in #71
• Save version information with flag by @matth2k in #72
• Parse escaped identifiers in verilog by @berkgokmen14 in #73
• Add CYCLE and ARG node types by @berkgokmen14 in #76
• Assign Verilog outputs in correct order by @matth2k in #78
• Bump version to 0.3 by @matth2k in #79

New Contributors

• @arnavm30 made their first contribution in #65

Full Changelog: v0.2.0...v0.3.0

v0.2.0

Here is some initial results on compiling the MCNC benchmarks from https://github.com/lsils/SCE-benchmarks/tree/main/MCNC/original

The binaries were built on Ubuntu 24.04.1 LTS