v0.8.0

What's Changed

• Add purge function for ASIC tech mapping by @matth2k in #154
• Add missing input by @matth2k in #155
• Update crate name for paper by @matth2k in #156
• Driver tool renaming by @matth2k in #157
• Some docs polishing by @matth2k in #158

Full Changelog: v0.7.2...v0.8.0

v0.7.2

What's Changed

• Add basic report for ASIC by @matth2k in #144
• Add ASIC area model by @matth2k in #145
• Add total cell count to report by @matth2k in #146
• Refactor driver optimization strategies by @matth2k in #147
• Add CellLang to parse-verilog tool by @matth2k in #149
• Salvage SVModule with duplicate ports on emission by @matth2k in #150
• Fix optcell args and BUS cost by @matth2k in #151
• Check that circuit is fully mapped by default by @matth2k in #152
• Add equiv checking script for ASIC flow by @matth2k in #153

Full Changelog: v0.7.1...v0.7.2

v0.7.1

What's Changed

• CellLang support multiple module outputs by @matth2k in #140
• Implement rest of PrimitiveTypes as rewrite rules by @matth2k in #141
• Implement most of the cells by @matth2k in #142
• Add rest of cells, refactor ASIC rewrites by @matth2k in #143

Full Changelog: v0.7.0...v0.7.1

v0.7.0

What's Changed

• Adjust build params for cellmap by @matth2k in #135
• New setup for macOS by @arnavm30 in #130
• Move setup.zsh to correct directory by @matth2k in #136
• Finish Verilog backend unification by @matth2k in #137
• Refactor frontend Verilog compilation by @matth2k in #138
• Add top-level ASIC tool by @matth2k in #139

Full Changelog: v0.6.3...v0.7.0

v0.6.3

What's Changed

• Add LUT1 to simlib by @matth2k in #125
• Fix node definitions in e-graph dumps by @matth2k in #126
• Update serialized node names for SmoothE by @matth2k in #127
• Generate more concise proofs by @matth2k in #128
• Revise README by @matth2k in #129
• Refactor driver in terms of new CircuitLang trait by @matth2k in #131
• Initial commit of ASIC tech mapping by @matth2k in #132
• Verilog emission refactor by @matth2k in #133
• Bump version by @matth2k in #134

Full Changelog: v0.6.2...v0.6.3

v0.6.2

What's Changed

• Add graph_dumps feature by @matth2k in #123
• Fix setup script for when build fails by @matth2k in #124

Full Changelog: v0.6.1...v0.6.2

v0.6.1

What's Changed

• Refactor runner limits into a BuildStrat by @matth2k in #118
• Add time progress bar by @matth2k in #119
• Fix wire decl for escaped names by @matth2k in #120
• Let CTRL+C interrupt e-graph build by @matth2k in #121
• Change how nets are named by @matth2k in #122

Full Changelog: v0.6.0...v0.6.1

v0.6.0 Rust 2024 Edition

Bump dependencies and Rust to last versions (#117)

v0.5.3

What's Changed

• Don't use SRL with Yosys by @matth2k in #113
• Fix calculating input size in reports by @matth2k in #114
• Add --reg-weight flag by @matth2k in #115

Full Changelog: v0.5.2...v0.5.3

v0.5.2 Bug Fixes

What's Changed

• Add VCC primitive by @matth2k in #110
• Full support for don't care values by @matth2k in #111
• Update verify() for misplaced integers by @matth2k in #112

Full Changelog: v0.5.1...v0.5.2