v0.7.2

What's Changed

• Add basic report for ASIC by @matth2k in #144
• Add ASIC area model by @matth2k in #145
• Add total cell count to report by @matth2k in #146
• Refactor driver optimization strategies by @matth2k in #147
• Add CellLang to parse-verilog tool by @matth2k in #149
• Salvage SVModule with duplicate ports on emission by @matth2k in #150
• Fix optcell args and BUS cost by @matth2k in #151
• Check that circuit is fully mapped by default by @matth2k in #152
• Add equiv checking script for ASIC flow by @matth2k in #153

Full Changelog: v0.7.1...v0.7.2