v0.7.0

matth2k released this 22 Apr 15:44

· 27 commits to main since this release

ebda942

What's Changed

Adjust build params for cellmap by @matth2k in #135
New setup for macOS by @arnavm30 in #130
Move setup.zsh to correct directory by @matth2k in #136
Finish Verilog backend unification by @matth2k in #137
Refactor frontend Verilog compilation by @matth2k in #138
Add top-level ASIC tool by @matth2k in #139

Full Changelog: v0.6.3...v0.7.0

Contributors

arnavm30 and matth2k

Assets 2