Working Branch PR for LLBP / Overriding #8
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dhschall
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Jun 10, 2025
…#2346) For a number of common instructions, gem5's built-in ARM disassembler doesn't print the instruction operands. This can be a bit of a headache when you don't want to use libcapstone, and are looking at instruction traces. Reproducer: test.S ``` .text .globl _start _start: ldr x30, [sp] ldr x30, [sp], gem5#16 str x30, [sp] str x30, [sp], gem5#16 ldp x10, x20, [x30] stp x10, x20, [x30] ldp w10, w20, [x30] stp w10, w20, [x30] ldp x10, x20, [x30], #-8 // post-index, negative stp x10, x20, [x30, gem5#16]! // pre-index, write-back ldp w10, w20, [x30, gem5#32] // pre-index, no write-back stp w10, w20, [x30], gem5#128 // post-index, positive dc zva, x17 dc cvac, x17 isb isb #10 dsb nsh dsb sy dsb #8 .long 0xff210110 // m5_op EXIT ``` ``` # Build binary aarch64-linux-gnu-gcc -c test.S -o test.o aarch64-linux-gnu-ld -o test.arm64 test.o -N -Ttext 0x10 -static # objdump disassembly aarch64-linux-gnu-objdump -D test.arm64 # gem5 disassembly ./build/ARM/gem5.opt configs/example/arm/baremetal.py --tarmac-gen --kernel test.arm64 | grep ' IT ' ```
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