serwb/s7serdes: Implement Width Expansion

Author: cklarhorst

liteiclink/serwb/s7serdes.py

@@ -20,11 +20,15 @@
 
 class _S7SerdesClocking(LiteXModule):
     def __init__(self, pads, mode="master", data_width=8):
-        assert data_width in [4,6,8] # valid serdese2 ddr rates
+        assert data_width in [4,6,8,10,14] # valid serdese2 ddr rates
+        if data_width>=10:
+            assert hasattr(pads, "tx_p"), "Width expansion can only be used for differential outputs"
         self.refclk = Signal()
 
         # # #
 
+        master_shiftin1  = Signal()
+        master_shiftin2  = Signal()
         # Master Mode.
         # ------------
         # Generate the linerate/10 clock. Slave will re-multiply it.
@@ -47,10 +51,34 @@ def __init__(self, pads, mode="master", data_width=8):
                     i_RST    = ResetSignal("sys"),
                     i_CLK    = ClockSignal(f"sys{data_width//2}x"),
                     i_CLKDIV = ClockSignal("sys"),
-                    **{f"i_D{i+1}" : converter.source.data[i] for i in range(data_width)},
+                    **{f"i_D{i+1}" : converter.source.data[i] for i in range(min(data_width,8))},
+                    i_SHIFTIN1 = master_shiftin1,
+                    i_SHIFTIN2 = master_shiftin2,
                     o_OQ     = self.refclk,
                 )
             ]
+            if data_width>=10:
+                slave_shiftout1 = Signal()
+                slave_shiftout2 = Signal()
+                self.specials += [
+                    Instance("OSERDESE2",
+                        p_DATA_WIDTH     = data_width,
+                        p_TRISTATE_WIDTH = 1,
+                        p_DATA_RATE_OQ   = "DDR",
+                        p_DATA_RATE_TQ   = "BUF",
+                        p_SERDES_MODE    = "SLAVE",
+
+                        i_OCE    = 1,
+                        i_RST    = ResetSignal("sys"),
+                        i_CLK    = ClockSignal(f"sys{data_width//2}x"),
+                        i_CLKDIV = ClockSignal("sys"),
+                        **{f"i_D{i+3}" : converter.source.data[i+8] for i in range(data_width-8)}, #d3-d8 see UG471:168
+                        o_SHIFTOUT1 = slave_shiftout1,
+                        o_SHIFTOUT2 = slave_shiftout2,
+                    )
+                ]
+                self.comb += [master_shiftin1.eq(slave_shiftout1),
+                              master_shiftin2.eq(slave_shiftout2)]
             if hasattr(pads, "clk_p"):
                 self.specials += DifferentialOutput(self.refclk, pads.clk_p, pads.clk_n)
             else:
@@ -69,7 +97,10 @@ def __init__(self, pads, mode="master", data_width=8):
 
 class _S7SerdesTX(LiteXModule):
     def __init__(self, pads, data_width=8):
-        assert data_width in [4,6,8] # valid serdese2 ddr rates
+        assert data_width in [4,6,8,10,14] # valid serdese2 ddr rates
+        if data_width>=10:
+            assert hasattr(pads, "tx_p"), "Width expansion can only be used for differential outputs"
+
         # Control
         self.idle  = idle  = Signal()
         self.comma = comma = Signal()
@@ -94,6 +125,8 @@ def __init__(self, pads, data_width=8):
         # -----------------------------
         self.data = data = Signal(data_width)
         data_serialized  = Signal()
+        master_shiftin1  = Signal()
+        master_shiftin2  = Signal()
         self.comb += data.eq(datapath.source.data)
         self.specials += [
             Instance("OSERDESE2",
@@ -107,10 +140,35 @@ def __init__(self, pads, data_width=8):
                 i_RST    = ResetSignal("sys"),
                 i_CLK    = ClockSignal(f"sys{data_width//2}x"),
                 i_CLKDIV = ClockSignal("sys"),
-                **{f"i_D{i+1}" : data[i] for i in range(data_width)},
+                **{f"i_D{i+1}" : data[i] for i in range(min(data_width,8))},
+                i_SHIFTIN1 = master_shiftin1,
+                i_SHIFTIN2 = master_shiftin2,
                 o_OQ     = data_serialized,
             )
         ]
+        if data_width>=10:
+            slave_shiftout1 = Signal()
+            slave_shiftout2 = Signal()
+            self.specials += [
+                Instance("OSERDESE2",
+                    p_DATA_WIDTH     = data_width,
+                    p_TRISTATE_WIDTH = 1,
+                    p_DATA_RATE_OQ   = "DDR",
+                    p_DATA_RATE_TQ   = "BUF",
+                    p_SERDES_MODE    = "SLAVE",
+
+                    i_OCE    = 1,
+                    i_RST    = ResetSignal("sys"),
+                    i_CLK    = ClockSignal(f"sys{data_width//2}x"),
+                    i_CLKDIV = ClockSignal("sys"),
+                    **{f"i_D{i+3}" : data[i+8] for i in range(data_width-8)}, #d3-d8 see UG471:168
+                    o_SHIFTOUT1 = slave_shiftout1,
+                    o_SHIFTOUT2 = slave_shiftout2,
+                )
+            ]
+            self.comb += [master_shiftin1.eq(slave_shiftout1),
+                          master_shiftin2.eq(slave_shiftout2)]
+        
         if hasattr(pads, "tx_p"):
             self.specials += DifferentialOutput(data_serialized, pads.tx_p, pads.tx_n)
         else:
@@ -120,7 +178,9 @@ def __init__(self, pads, data_width=8):
 
 class _S7SerdesRX(LiteXModule):
     def __init__(self, pads, data_width=8):
-        assert data_width in [4,6,8] # valid serdese2 ddr rates
+        assert data_width in [4,6,8,10,14] # valid serdese2 ddr rates
+        if data_width>=10:
+            assert hasattr(pads, "rx_p"), "Width expansion can only be used for differential outputs"
         # Control.
         self.delay_rst = delay_rst = Signal()
         self.delay_inc = delay_inc = Signal()
@@ -142,6 +202,8 @@ def __init__(self, pads, data_width=8):
         # ----------------------------
         data_nodelay      = Signal()
         data_delayed      = Signal()
+        master_shiftout1  = Signal()
+        master_shiftout2  = Signal()
         self.data = data  = Signal(data_width)
 
         if hasattr(pads, "rx_p"):
@@ -183,9 +245,37 @@ def __init__(self, pads, data_width=8):
                 i_CLKB    =~ClockSignal(f"sys{data_width//2}x"),
                 i_CLKDIV  = ClockSignal("sys"),
                 i_BITSLIP = shift_inc,
-                **{f"o_Q{data_width-i}" : data[i] for i in range(data_width)},
+                **{f"o_Q{i+1}" : data[data_width-i-1] for i in range(min(8,data_width))},
+                o_SHIFTOUT1 = master_shiftout1,
+                o_SHIFTOUT2 = master_shiftout2,
             )
         ]
+        if data_width>=10:
+            slave_shiftin1 = Signal()
+            slave_shiftin2 = Signal()
+            remaining_bits = data_width-8
+            self.specials += [
+                Instance("ISERDESE2",
+                p_DATA_WIDTH     = data_width,
+                p_DATA_RATE      = "DDR",
+                p_SERDES_MODE    = "SLAVE",
+                p_INTERFACE_TYPE = "NETWORKING",
+                p_NUM_CE         = 1,
+                p_IOBDELAY       = "IFD",
+
+                i_CE1     = 1,
+                i_RST     = ResetSignal("sys"),
+                i_CLK     = ClockSignal(f"sys{data_width//2}x"),
+                i_CLKB    =~ClockSignal(f"sys{data_width//2}x"),
+                i_CLKDIV  = ClockSignal("sys"),
+                i_BITSLIP = shift_inc,
+                i_SHIFTIN1 = slave_shiftin1,
+                i_SHIFTIN2 = slave_shiftin2,
+                **{f"o_Q{i+3}" : data[remaining_bits-i-1] for i in range(remaining_bits)}, #d3-d8 see UG471:155
+                )
+            ]
+            self.comb += [slave_shiftin1.eq(master_shiftout1),
+                          slave_shiftin2.eq(master_shiftout2)]
 
         # Datapath.
         # ---------