Added missing reg on BUFGCE_DIV output

Frédéric REQUIN · Frédéric REQUIN · commit 290bf714552f · 2022-06-02T20:01:38.000+02:00
diff --git a/BUFGCE_DIV.v b/BUFGCE_DIV.v
@@ -19,10 +19,10 @@ module BUFGCE_DIV
     parameter   [0:0] IS_I_INVERTED   = 1'b0
 )
 (
-    input  I,
-    input  CE,
-    input  CLR,
-    output O /* verilator clocker */
+    input      I,
+    input      CE,
+    input      CLR,
+    output reg O /* verilator clocker */
 );
 
     wire       w_CLK = I ^ IS_I_INVERTED;

Original file line number	Diff line number	Diff line change
`@@ -19,10 +19,10 @@ module BUFGCE_DIV`
`19`	`19`	`parameter [0:0] IS_I_INVERTED = 1'b0`
`20`	`20`	`)`
`21`	`21`	`(`
`22`		`- input I,`
`23`		`- input CE,`
`24`		`- input CLR,`
`25`		`- output O /* verilator clocker */`
	`22`	`+ input I,`
	`23`	`+ input CE,`
	`24`	`+ input CLR,`
	`25`	`+ output reg O /* verilator clocker */`
`26`	`26`	`);`
`27`	`27`
`28`	`28`	`wire w_CLK = I ^ IS_I_INVERTED;`