v0.3.3.1

Last stable release of 0.3

Improved Adaptive Filter.
Added random signals.
Improved pre-compute simulator.

0.3.3

Last stable release of 0.3

Improved Adaptive Filter.
Added random signals.
Improved pre-compute simulator.

v0.3.2

Major code refactoring with

• improved python simulators.
• quadrature analog system and digital control.

v0.2.3

Major additions with the circuit submodule, enabling circuit simulations in ngspice.

Fix

new fix (#82)

Co-authored-by: Hampus Malmberg <malmberg@isi.ee.ethz.ch>

v0.2.0

Major structural changes. Mainly motivated by improving simulators and filter coefficient computations to support switch-cap digital control simulations.

Specifically,

• digital clock to aid the simulator and digital estimator computation
• digital control and derived classes have a new interface to support digital clock, i.e, DigitalControl(..., clock, ...).
• Simulator
  • Analytical simulator implemented using SymPy
  • Mpmath simulator implemented using mpmath
  • Two Numerical simulators implemented using NumPy
    • Full simulator the pervious default simulator.
    • pre-computed simulator same as Full simulator with the distinction that the control contributions are pre-computed.
  • The previous default StateSpaceSimulator class has been replaced by the get_simulator function. The simulation backend is chosen by passing an instance of SimulatorType.
  • The simulation clock period Ts is replaced by the digital clock object and thus all simulator classes and the factory function get_simulation(..., clock, ...) is now instantiated with a clock determining the sample times.
• DigitalEstimator
  • The default DigitalEstimator changes it's name to BatchEstimator
  • an additional filter computation backend implemented with mpmath
• Improved care implementation using SymPy instead of SciPy.
• cbadc.specification.get_chain_of_integrator and cbadc.specification.get_leap_frog a computation aid to dimension chain-of-integrators and leap-frog analog-frontends to meet ENOB and BW specifications

Added verilog-ams circuit-level submodule

Such that circuit-level implementations can be

• constructed in Verilog-ams
• the resulting filter coefficients can be computed
• the resulting analog frontends can be simulated.

FoM

Included Figures of merit module and Murmann ADC Survey

Updated Simulator and Estimator

This release made several enhancements concerning the state space simulator and digital estimator.

These were necessary for the switched capacitor simulations.

v0.1.3

added harmonic distortion (#49)

v0.1.2: Feature/fixed point (#47)

* added fixed point FIR Filter arithmetics

* added vscode settings

* and gitignore

* fixed point arithmetics

* modified for documentation

* updated image