update to v1.14.2 · mshr-h/vscode-verilog-hdl-support@416807d

Expected '!==' and instead saw '!='

Import name `child_process` must match one of the following formats: camelCase, PascalCase

Expected '===' and instead saw '=='

Missing semicolon

Unexpected constant condition

'process' is not defined

Expected '===' and instead saw '=='

Expected '===' and instead saw '=='

Expected '!==' and instead saw '!='

Import name `child_process` must match one of the following formats: camelCase, PascalCase

Provide feedback