Add parameters back into Module instantiation · mshr-h/vscode-verilog-hdl-support@bb20dd4

Expected '!==' and instead saw '!='

Import name `child_process` must match one of the following formats: camelCase, PascalCase

Expected '===' and instead saw '=='

Missing semicolon

Unexpected constant condition

'process' is not defined

Expected '===' and instead saw '=='

Expected '===' and instead saw '=='

Expected '!==' and instead saw '!='

Import name `child_process` must match one of the following formats: camelCase, PascalCase

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