update to v1.16.0 · mshr-h/vscode-verilog-hdl-support@2677b56

Expected '!==' and instead saw '!='

Expected '===' and instead saw '=='

Unexpected constant condition

'process' is not defined

Expected '===' and instead saw '=='

Expected '===' and instead saw '=='

Expected '!==' and instead saw '!='

Import name `child_process` must match one of the following formats: camelCase, PascalCase

Import name `child_process` must match one of the following formats: camelCase, PascalCase

'BufferEncoding' is not defined

Provide feedback