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1. device_modeling device_modeling Public

   Forked from os-fpga/device_modeling

   Verilog

2. cva6 cva6 Public

   Forked from openhwgroup/cva6

   The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

   Assembly

3. core-v-verif core-v-verif Public

   Forked from openhwgroup/core-v-verif

   Functional verification project for the CORE-V family of RISC-V cores.

   Assembly

4. pulpissimo pulpissimo Public

   Forked from pulp-platform/pulpissimo

   This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

   SystemVerilog