Add ALU to ALU bypass in superscalar mode #2951
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core/issue_read_operands.sv
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| @@ -813,6 +851,14 @@ module issue_read_operands | |||
| if (issue_instr_valid_i[i] && !fu_busy[i]) begin | |||
| if (!stall_raw[i]) begin | |||
| issue_ack[i] = 1'b1; | |||
| // For now keep this as is, we cannot do inter dual-issue forwarding | |||
| if (i > 0) begin | |||
| if ((issue_instr_i[i].rd[4:0] == issue_instr_i[i-1].rd[4:0]) && (issue_instr_i[i].rd[4:0] != '0)) begin | |||
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Are these [4:0] slicing needed?
Shouldn’t this block of conditions be already managed inside stall_raw[1] instead of here?
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@JeanRochCoulon would it be possible to understand what is failing in the FPGA flow in the CI? I tried to run an FPGA synth locally and it arrives at the end, but I cannot reproduce the CI setup one-to-one. |
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Co-authored-by: Gianmarco Ottavi <ottavig91@gmail.com>
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This PR introduce ALU to ALU bypass to allow dual issue of consecutive ALU instructions with a RAW dependency.
The ALUs are now instantiated inside a wrapper module, which provides either a single ALU for the scalar configuration or two ALUs with bypass logic in the superscalar scenario.
When two ALUs are instantiated, CPOP is carried out separately to avoid timing degradation.
At the moment the bypass is activated whenver
SuperscalarEn=1. If a dedicated parameter is preferred to decouple the two features I can add it.