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    53 repositories

    • IHP-Open-PDK

      Public
      130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
      HTML
      •
      Apache License 2.0
      •105•1•3•2•Updated Aug 25, 2025Aug 25, 2025

    • IIC-OSIC-TOOLS

      Public
      IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
      circuitsicdigital-designmicroelectronicsanalog-designmixed-signal-chips
      Shell
      •
      Apache License 2.0
      •121•645•28•0•Updated Aug 25, 2025Aug 25, 2025

    • klayout-align-tool

      Public
      GNU General Public License v3.0
      •1•6•0•0•Updated Aug 23, 2025Aug 23, 2025

    • klayout-move-tool

      Public
      KLayout plugin providing an efficient tool to move shapes or instances
      GNU General Public License v3.0
      •0•1•0•0•Updated Aug 23, 2025Aug 23, 2025

    • analog-circuit-design

      Public
      Course material for a basic hands-on analog circuit design course with IC emphasis
      Jupyter Notebook
      •
      Apache License 2.0
      •24•138•2•1•Updated Jul 31, 2025Jul 31, 2025

    • SG13G2_ASIC-Design-Template

      Public
      SG13G2_ASIC-Design-Template
      Python
      •5•1•0•0•Updated Jul 28, 2025Jul 28, 2025

    • SG13G2_ATBS-ADC

      Public
      Author: Simon Dorrer, 2024 / 2025, Johannes Kepler University (JKU) Linz, Austria, Institute for Integrated Circuits and Quantum Computing (IICQC) / Institute of Signal Processing (ISP). This ATBS-ADC has been designed in the context of a Master's thesis, it is published on https://epub.jku.at/obvulihs/content/titleinfo/12118473.
      Verilog
      •
      Apache License 2.0
      •0•6•0•0•Updated Jul 27, 2025Jul 27, 2025

    • osic-tool-collection

      Public
      Collection of useful scripts for Open-Source IC Design
      Python
      •
      Apache License 2.0
      •1•4•0•0•Updated Jul 16, 2025Jul 16, 2025

    • openlane2

      Public
      The next generation of OpenLane, rewritten from scratch with a modular architecture
      Python
      •
      Apache License 2.0
      •66•1•0•1•Updated Jul 5, 2025Jul 5, 2025

    • .github

      Public
      1•1•0•0•Updated Apr 10, 2025Apr 10, 2025

    • Hdl21

      Public
      Hardware Description Library
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •18•0•0•0•Updated Apr 10, 2025Apr 10, 2025

    • osic-multitool

      Public
      JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.
      magicnetgenngspicelvsopenlanesky130xschem
      Verilog
      •
      Apache License 2.0
      •17•68•2•0•Updated Mar 28, 2025Mar 28, 2025

    • SKY130_SAR-ADC1

      Public
      Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license
      adcmixed-signalsky130icdesign
      Verilog
      •
      Apache License 2.0
      •17•42•0•0•Updated Mar 13, 2025Mar 13, 2025

    • sky130_adc_202311

      Public
      PLSQL
      •
      Apache License 2.0
      •100•7•0•0•Updated Mar 6, 2025Mar 6, 2025

    • cace

      Public
      Circuit Automatic Characterization Engine
      Python
      •
      Apache License 2.0
      •16•3•0•0•Updated Feb 7, 2025Feb 7, 2025

    • klayout-pex

      Public
      Parasitic Extraction for KLayout
      Python
      •
      GNU General Public License v3.0
      •5•2•0•0•Updated Jan 16, 2025Jan 16, 2025

    • padring

      Public
      A padring generator for ASICs
      C++
      •
      ISC License
      •11•1•0•0•Updated Dec 27, 2024Dec 27, 2024

    • klayout-pex-website

      Public
      Website and Documentation for klayout-pex
      Shell
      •
      Apache License 2.0
      •2•0•0•0•Updated Dec 10, 2024Dec 10, 2024

    • BTLE

      Public
      Bluetooth Low Energy (BLE) packet sniffer and transmitter for both standard and non standard (raw bit) based on Software Defined Radio (SDR).
      Jupyter Notebook
      •
      Apache License 2.0
      •149•1•0•0•Updated Dec 2, 2024Dec 2, 2024

    • Circuit-Designers-Etiquette

      Public
      A set of rules and recommendations for analog and digital circuit designers.
      Apache License 2.0
      •1•29•3•0•Updated Nov 4, 2024Nov 4, 2024

    • ttihp-0p2-hpretl-minilogix

      Public
      A simple 8b input, 8b output freely programmable logic block with optional selectable feedback.
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Nov 2, 2024Nov 2, 2024

    • ttihp0p2-um-hpretl-spi

      Public
      Simple SPI-based register file (for the testing the flow)
      Verilog
      •
      Apache License 2.0
      •1•2•0•0•Updated Oct 31, 2024Oct 31, 2024

    • mpw8-submission

      Public
      MPW-8 tapeout submission containing mixed-signal circuit blocks in SKY130
      Verilog
      •
      Apache License 2.0
      •1•6•0•1•Updated Sep 3, 2024Sep 3, 2024

    • Vlsir

      Public
      Interchange formats for chip design.
      TypeScript
      •
      BSD 3-Clause "New" or "Revised" License
      •12•0•0•1•Updated Aug 11, 2024Aug 11, 2024

    • IIC-RALF

      Public
      Reinforcement learning assisted analog layout design flow.
      Python
      •
      Apache License 2.0
      •12•29•0•0•Updated Jul 29, 2024Jul 29, 2024

    • ioplace_parser

      Public
      Antlr4-based parser for the input files to OpenLane custom IO placers.
      Python
      •6•0•0•1•Updated Jul 5, 2024Jul 5, 2024

    • tt05-analog-test

      Public
      Analog test macro (500kHz ring oscillator, 3-bit DAC) for TinyTapeout 05.
      Tcl
      •
      Apache License 2.0
      •3•5•1•0•Updated Jun 14, 2024Jun 14, 2024

    • jku-sfl-test-cells

      Public
      Flicker noise test cells for the IHP Open-Source PDK (SG13G2) for the MPW Tape-out May 2024.
      Apache License 2.0
      •0•0•0•0•Updated Jun 3, 2024Jun 3, 2024

    • kvosid_336004_ss24

      Public
      Course material for 336.004 (Prof. Pretl) in SS24 at JKU
      Python
      •1•0•0•0•Updated May 28, 2024May 28, 2024

    • SKY130_PLL1

      Public
      Implementation of a Sub-Sampling PLL targeting SerDes Applications in SKYWATER PDK 130nm process
      Verilog
      •3•7•0•0•Updated Apr 23, 2024Apr 23, 2024