Merge pull request #427 from os-fpga/EDA-3187-add-setup-lec-sim

EDA-3187 added setup_lec_sim for Briey

Author: NadeemYaseen

RTL_testcases/opensource_with_testbench/Briey_soc/raptor_run.sh

@@ -10,8 +10,8 @@ ip_name="" #design_level
 tool_name="iverilog" 
 
 #simulation stages
-post_synth_sim=false 
-post_route_sim=false 
+post_synth_sim=true 
+post_route_sim=true 
 bitstream_sim=false
 
 #raptor options
@@ -200,7 +200,7 @@ parse_cga exit 1; }
     [ -z "$strategy" ] && echo "" || echo "synthesize $strategy">>raptor_tcl.tcl  
 
     if [ "$post_synth_sim" == true ] || [ "$post_route_sim" == true ] || [ "$bitstream_sim" == true ]; then
-        echo "setup_lec_sim 2 2">>raptor_tcl.tcl
+        echo "setup_lec_sim 10 2">>raptor_tcl.tcl
     else
         echo ""
     fi