Merge pull request #426 from os-fpga/EDA-3187-add-setup-lec-sim

EDA-3187 added setup_lec_sim for BOOT_CLOCK_primitive_inst

Author: NadeemYaseen

RTL_testcases/RS_FPGA_PRIMITIVES_new/BOOT_CLOCK_primitive_inst/raptor_run.sh

@@ -260,6 +260,10 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "clear_simulation_files">>raptor_tcl.tcl 
+    echo "setup_lec_sim">>raptor_tcl.tcl
+    echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

RTL_testcases/RS_FPGA_PRIMITIVES_new/BOOT_CLOCK_primitive_inst/rtl/BOOT_CLOCK_primitive_inst.v

@@ -1,7 +1,7 @@
 module BOOT_CLOCK_primitive_inst (
   input wire clk1,       // Source clock domain clock
   input wire async_signal, // Asynchronous signal to be synchronized
-  output reg sync_signal, // Synchronized signal
+  output reg sync_signal = 0, // Synchronized signal
   output reg O_BOOT_CLOCK // Clock output
 );