Merge pull request #447 from os-fpga/task/EDA-3187/add_setup_lec_sim

Task/eda 3187/add setup lec sim

Author: NadeemYaseen

RTL_testcases/RTL_Benchmarks_Gap_Analysis/fixed_point_arithmetic_parameterized/raptor_run.sh

@@ -261,6 +261,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

RTL_testcases/RTL_Benchmarks_Gap_Analysis/fixed_point_arithmetic_parameterized/rtl/qdiv.v

@@ -36,7 +36,7 @@ module qdiv(
 	reg [N-1:0] dividend_copy;
 	reg [2*(N-1)-1:0] divider_copy;
 
-	reg [5:0] bit; 
+	reg [5:0] bt; 
 	reg done;
 
 	initial done = 1;
@@ -49,7 +49,7 @@ module qdiv(
 		if( done && start ) begin
 
 			done <= 1'b0;
-			bit <= N+Q-2;
+			bt <= N+Q-2;
 			quotient <= 0;
 			dividend_copy <= {1'b0,dividend[N-2:0]};
 
@@ -69,18 +69,18 @@ module qdiv(
 				//subtract
 				dividend_copy <= dividend_copy - divider_copy;
 				//set quotient
-				quotient[bit] <= 1'b1;
+				quotient[bt] <= 1'b1;
 			end
 
 			//reduce divisor
 			divider_copy <= divider_copy >> 1;
 
 			//stop condition
-			if(bit == 0)
-				done <= 1'b1;
-				
+			if(bt == 0)
+				done <= 1'b1;
+				
 			//reduce bit counter
-			bit <= bit - 1;	
+			bt <= bt - 1;	
 		end
 	end
 endmodule

RTL_testcases/RTL_Benchmarks_Gap_Analysis/fpga-median/raptor_run.sh

@@ -186,7 +186,7 @@ parse_cga exit 1; }
     # [ -z "$ip_name" ] && echo "add_library_ext .v .sv">>raptor_tcl.tcl || echo "" 
     [ -z "$ip_name" ] && echo "add_design_file ./rtl/common_network.v">>raptor_tcl.tcl
     [ -z "$ip_name" ] && echo "add_design_file ./rtl/dff_3_pipe.v">>raptor_tcl.tcl
-    [ -z "$ip_name" ] && echo "add_design_file ./rtl/dual_port_ram.v">>raptor_tcl.tcl
+    # [ -z "$ip_name" ] && echo "add_design_file ./rtl/dual_port_ram.v">>raptor_tcl.tcl
     [ -z "$ip_name" ] && echo "add_design_file ./rtl/median.v">>raptor_tcl.tcl
     [ -z "$ip_name" ] && echo "add_design_file ./rtl/node.v">>raptor_tcl.tcl
     [ -z "$ip_name" ] && echo "add_design_file ./rtl/pixel_network.v">>raptor_tcl.tcl
@@ -264,6 +264,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

RTL_testcases/test_raptor_batch_options/fsm_encoding_binary/raptor_run.sh

@@ -258,6 +258,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

RTL_testcases/test_raptor_batch_options/fsm_encoding_onehot/raptor_run.sh

@@ -258,6 +258,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl