Merge pull request #418 from os-fpga/rtl_update

updated rtl and testbench for primitive_example_design_14 and primiti…

Author: NadeemYaseen

RTL_testcases/RS_Primitive_example_designs/primitive_example_design_14/rtl/primitive_example_design_14.v

@@ -17,9 +17,13 @@ reg [WIDTH-1:0] data_out_flop;
 reg enable, pll_lock;
 wire i1_ibuf;
 reg [WIDTH-1:0] dff_out;
+wire clk_in_ibuf;
+wire clk_in_clkbuf;
+wire pll_clk;
+wire clk_pll_in;
 
-I_BUF i_buf_inst1 (.I(clk_in),.EN(en),.O(clk_in_ibuf));
-I_BUF i_buf_inst2 (.I(i1),.EN(en),.O(i1_ibuf));
+I_BUF i_buf_inst1 (.I(clk_in),.EN(1'b1),.O(clk_in_ibuf));
+I_BUF i_buf_inst2 (.I(i1),.EN(1'b1),.O(i1_ibuf));
 CLK_BUF clk_buf_inst (.I(clk_in_ibuf), .O(clk_in_clkbuf));
 
 I_SERDES inst(

RTL_testcases/RS_Primitive_example_designs/primitive_example_design_14/sim/co_sim_tb/co_sim_primitive_example_design_14.v

@@ -6,9 +6,8 @@ module co_sim_primitive_example_design_14;
   reg  clk_in;
   reg  reset;
   reg  i1;
-  reg  i2;
+  reg  [WIDTH-1:0] i2;
   wire [WIDTH-1:0] data_out,data_out_netlist;
-  reg  RX_RST;
   reg  BITSLIP_ADJ;
   wire  CLK_OUT,CLK_OUT_netlist;
   wire  DATA_VALID,DATA_VALID_netlist;
@@ -18,22 +17,21 @@ module co_sim_primitive_example_design_14;
 
 	integer mismatch=0;
 
-  primitive_example_design_14 # (.WIDTH(WIDTH)) golden (.clk_in(clk_in),.reset(reset),.i1(i1),.i2(i2),.data_out(data_out),.RX_RST(RX_RST),.BITSLIP_ADJ(BITSLIP_ADJ),.CLK_OUT(CLK_OUT),.DATA_VALID(DATA_VALID),.DPA_LOCK(DPA_LOCK),.DPA_ERROR(DPA_ERROR),.PLL_CLK(PLL_CLK));
+  primitive_example_design_14 # (.WIDTH(WIDTH)) golden (.clk_in(clk_in),.reset(reset),.i1(i1),.i2(i2),.data_out(data_out),.BITSLIP_ADJ(BITSLIP_ADJ),.CLK_OUT(CLK_OUT),.DATA_VALID(DATA_VALID),.DPA_LOCK(DPA_LOCK),.DPA_ERROR(DPA_ERROR),.PLL_CLK(PLL_CLK));
   `ifdef PNR
-  primitive_example_design_14_post_route netlist (.clk_in(clk_in),.reset(reset),.i1(i1),.i2(i2),.data_out(data_out_netlist),.RX_RST(RX_RST),.BITSLIP_ADJ(BITSLIP_ADJ),.CLK_OUT(CLK_OUT_netlist),.DATA_VALID(DATA_VALID_netlist),.DPA_LOCK(DPA_LOCK_netlist),.DPA_ERROR(DPA_ERROR_netlist),.PLL_CLK(PLL_CLK));
+  primitive_example_design_14_post_route netlist (.clk_in(clk_in),.reset(reset),.i1(i1),.i2(i2),.data_out(data_out_netlist),.BITSLIP_ADJ(BITSLIP_ADJ),.CLK_OUT(CLK_OUT_netlist),.DATA_VALID(DATA_VALID_netlist),.DPA_LOCK(DPA_LOCK_netlist),.DPA_ERROR(DPA_ERROR_netlist),.PLL_CLK(PLL_CLK));
   `else
-  primitive_example_design_14_post_synth netlist (.clk_in(clk_in),.reset(reset),.i1(i1),.i2(i2),.data_out(data_out_netlist),.RX_RST(RX_RST),.BITSLIP_ADJ(BITSLIP_ADJ),.CLK_OUT(CLK_OUT_netlist),.DATA_VALID(DATA_VALID_netlist),.DPA_LOCK(DPA_LOCK_netlist),.DPA_ERROR(DPA_ERROR_netlist),.PLL_CLK(PLL_CLK));
+  primitive_example_design_14_post_synth netlist (.clk_in(clk_in),.reset(reset),.i1(i1),.i2(i2),.data_out(data_out_netlist),.BITSLIP_ADJ(BITSLIP_ADJ),.CLK_OUT(CLK_OUT_netlist),.DATA_VALID(DATA_VALID_netlist),.DPA_LOCK(DPA_LOCK_netlist),.DPA_ERROR(DPA_ERROR_netlist),.PLL_CLK(PLL_CLK));
   `endif
 
   always #1 clk_in = !clk_in;
   always #2.5 PLL_CLK = !PLL_CLK;
 
   initial begin
-    {clk_in,reset,i1,i2,RX_RST,BITSLIP_ADJ,PLL_CLK}<=0;
+    {clk_in,reset,i1,i2,BITSLIP_ADJ,PLL_CLK}<=0;
 
     repeat(5)@(negedge clk_in);
     reset<=1;
-    RX_RST<=1;
     compare();
     repeat(5)@(negedge clk_in);
     // BITSLIP_ADJ<=1;
@@ -46,13 +44,13 @@ module co_sim_primitive_example_design_14;
       i2<=$random();
       compare();
     end
-    RX_RST<=0;
+    reset<=0;
     repeat(2)@(negedge clk_in) begin
       i1<=$random();
       i2<=$random();
       compare();
     end
-    RX_RST<=1;
+    reset<=1;
     repeat(2000)@(negedge clk_in) begin
       i1<=$random();
       i2<=$random();

RTL_testcases/RS_Primitive_example_designs/primitive_example_design_6/rtl/primitive_example_design_6.v

@@ -14,6 +14,8 @@ wire [1:0] i_buf_out;
 wire rst_i_buf_out;
 wire clk_buf_out;
 wire i_clk_buf_out;
+wire oddr_in;
+wire o_buf_ds_in;
 
 I_BUF i_buf_inst (.I(clk),.EN(ibuf_oe1),.O(i_clk_buf_out));
 CLK_BUF clk_buf_inst (.I(i_clk_buf_out), .O(clk_buf_out));

RTL_testcases/RS_Primitive_example_designs/primitive_example_design_6/sim/co_sim_tb/co_sim_primitive_example_design_6.v

@@ -9,16 +9,17 @@ module co_sim_primitive_example_design_6;
   reg  ibuf_oe3;
   reg  ibuf_oe4;
   reg  oddr_en;
+  wire q,q_netlist;
   wire  q_p,q_p_netlist;
   wire  q_n,q_n_netlist;
 
 	integer mismatch=0;
 
-  primitive_example_design_6 golden (.in(in),.clk(clk),. rst( rst),.ibuf_oe1(ibuf_oe1),.ibuf_oe2(ibuf_oe2),.ibuf_oe3(ibuf_oe3),.ibuf_oe4(ibuf_oe4),.oddr_en(oddr_en),.q_p(q_p),.q_n(q_n));
+  primitive_example_design_6 golden (.in(in),.clk(clk),. rst( rst),.ibuf_oe1(ibuf_oe1),.ibuf_oe2(ibuf_oe2),.ibuf_oe3(ibuf_oe3),.ibuf_oe4(ibuf_oe4),.oddr_en(oddr_en),.q(q),.q_p(q_p),.q_n(q_n));
   `ifdef PNR
-  primitive_example_design_6_post_route netlist (.in(in),.clk(clk),. rst( rst),.ibuf_oe1(ibuf_oe1),.ibuf_oe2(ibuf_oe2),.ibuf_oe3(ibuf_oe3),.ibuf_oe4(ibuf_oe4),.oddr_en(oddr_en),.q_p(q_p_netlist),.q_n(q_n_netlist));
+  primitive_example_design_6_post_route netlist (.in(in),.clk(clk),. rst( rst),.ibuf_oe1(ibuf_oe1),.ibuf_oe2(ibuf_oe2),.ibuf_oe3(ibuf_oe3),.ibuf_oe4(ibuf_oe4),.oddr_en(oddr_en),.q(q_netlist),.q_p(q_p_netlist),.q_n(q_n_netlist));
   `else
-  primitive_example_design_6_post_synth netlist (.in(in),.clk(clk),. rst( rst),.ibuf_oe1(ibuf_oe1),.ibuf_oe2(ibuf_oe2),.ibuf_oe3(ibuf_oe3),.ibuf_oe4(ibuf_oe4),.oddr_en(oddr_en),.q_p(q_p_netlist),.q_n(q_n_netlist));
+  primitive_example_design_6_post_synth netlist (.in(in),.clk(clk),. rst( rst),.ibuf_oe1(ibuf_oe1),.ibuf_oe2(ibuf_oe2),.ibuf_oe3(ibuf_oe3),.ibuf_oe4(ibuf_oe4),.oddr_en(oddr_en),.q(q_netlist),.q_p(q_p_netlist),.q_n(q_n_netlist));
   `endif
 
   always #1 clk = !clk ;
@@ -73,12 +74,12 @@ module co_sim_primitive_example_design_6;
   end
 
   task compare();
-  	if(q_n !== q_n_netlist || q_p !== q_p_netlist) begin
-    	$display("Data Mismatch. Golden q_n: %0d, Netlist q_n: %0d, Golden q_p: %0d, Netlist q_p: %0d, Time: %0t", q_n, q_n_netlist,q_p,q_p_netlist,$time);
+  	if(q_n !== q_n_netlist || q_p !== q_p_netlist || q !== q_netlist ) begin
+    	$display("Data Mismatch. Golden q_n: %0d, Netlist q_n: %0d, Golden q_p: %0d, Netlist q_p: %0d, Golden q: %0d, Netlist q: %0d, Time: %0t", q_n, q_n_netlist,q_p,q_p_netlist,q,q_netlist,$time);
     	mismatch = mismatch+1;
  	  end
   	else
-  		$display("Data Matched. Golden q_n: %0d, Netlist q_n: %0d, Golden q_p: %0d, Netlist q_p: %0d, Time: %0t", q_n, q_n_netlist,q_p,q_p_netlist,$time);
+  		$display("Data Matched. Golden q_n: %0d, Netlist q_n: %0d, Golden q_p: %0d, Netlist q_p: %0d, Golden q: %0d, Netlist q: %0d, Time: %0t", q_n, q_n_netlist,q_p,q_p_netlist,q,q_netlist,$time);
   endtask
 
   initial begin