Merge pull request #417 from os-fpga/example_designs

updated RTL of primitive_example_design_14 and primitive_example_desi…

Author: NadeemYaseen

RTL_testcases/RS_Primitive_example_designs/primitive_example_design_14/rtl/primitive_example_design_14.v

@@ -3,9 +3,8 @@ module primitive_example_design_14
   input clk_in,
   input reset,
   input i1,
-  input i2,
+  input [WIDTH-1:0] i2,
   output reg [WIDTH-1:0] data_out,
-  input RX_RST,
   input BITSLIP_ADJ,
   output CLK_OUT,
   output DATA_VALID,
@@ -14,45 +13,57 @@ module primitive_example_design_14
   input PLL_CLK
 );
 
-wire data_in;
 reg [WIDTH-1:0] data_out_flop;
 reg enable, pll_lock;
+wire i1_ibuf;
+reg [WIDTH-1:0] dff_out;
+
+I_BUF i_buf_inst1 (.I(clk_in),.EN(en),.O(clk_in_ibuf));
+I_BUF i_buf_inst2 (.I(i1),.EN(en),.O(i1_ibuf));
+CLK_BUF clk_buf_inst (.I(clk_in_ibuf), .O(clk_in_clkbuf));
 
 I_SERDES inst(
-.D(data_in),
-.RST(RX_RST),
+.D(i1_ibuf),
+.RST(reset),
 .BITSLIP_ADJ(BITSLIP_ADJ),
 .EN(enable),
-.CLK_IN(clk_in),
+.CLK_IN(clk_in_clkbuf),
 .CLK_OUT(CLK_OUT),
 .Q(data_out_flop),
 .DATA_VALID(DATA_VALID),
 .DPA_LOCK(DPA_LOCK),
 .DPA_ERROR(DPA_ERROR),
 .PLL_LOCK(pll_lock),
-.PLL_CLK(PLL_CLK)
+.PLL_CLK(pll_clk)
+);
+
+PLL #(.PLL_MULT(50), .PLL_DIV(1), .PLL_POST_DIV(17)) clk_pll_gen0 (
+  .PLL_EN(1'b1),
+  .CLK_IN(clk_pll_in),
+  .CLK_OUT(pll_clk),
+  .LOCK(pll_lock)
 );
 
-assign data_in = i1*i2; 
+BOOT_CLOCK boot_clk_inst (clk_pll_in);
+
+assign data_out = (dff_out + i2) * (dff_out - i2); 
 
-always @ (posedge clk_in or negedge reset)
+always @ (posedge clk_in_clkbuf or negedge reset)
   begin
   if(!reset) begin
    enable <= 1'b0;
-   pll_lock <= 1'b0;
   end 
   else begin
   enable <= 1'b1;
-  pll_lock <= 1'b1;
   end
  end
 
-always @ (posedge clk_in or negedge reset)
+always @ (posedge clk_in_clkbuf or negedge reset)
  begin
   if(!reset)
-    data_out <= 0;
+    dff_out <= 0;
   else 
-    data_out <= data_out_flop;
+    dff_out <= data_out_flop;
  end
 
 endmodule

RTL_testcases/RS_Primitive_example_designs/primitive_example_design_6/rtl/primitive_example_design_6.v

@@ -1,9 +1,10 @@
-module primitive_example_design_6(clk,in,rst,q_p,q_n,oddr_en,ibuf_oe1,ibuf_oe2,ibuf_oe3,ibuf_oe4);
+module primitive_example_design_6(clk,in,rst,q,q_p,q_n,oddr_en,ibuf_oe1,ibuf_oe2,ibuf_oe3,ibuf_oe4);
 
 input [1:0] in;
 input clk, rst;
 input ibuf_oe1,ibuf_oe2,ibuf_oe3,ibuf_oe4;
 input oddr_en;
+output q;
 output q_p;
 output q_n;
 
@@ -16,14 +17,15 @@ wire i_clk_buf_out;
 
 I_BUF i_buf_inst (.I(clk),.EN(ibuf_oe1),.O(i_clk_buf_out));
 CLK_BUF clk_buf_inst (.I(i_clk_buf_out), .O(clk_buf_out));
-O_DDR iddr_ist1 (.D(i_buf_out),.R(rst_i_buf_out),.E(oddr_en),.C(clk_buf_out),.Q(oddr_out));
+O_DDR iddr_ist1 (.D(oddr_in),.R(rst_i_buf_out),.E(oddr_en),.C(clk_buf_out),.Q(q));
 
-O_BUFT_DS o_buft_inst1 (.I(dffre_out),.O_N(q_n),.O_P(q_p),.T(1'b1));
+O_BUFT_DS o_buft_inst1 (.I(o_buf_ds_in),.O_N(q_n),.O_P(q_p),.T(1'b1));
 
 I_BUF ibuf_inst1 (.I(in[0]),.EN(ibuf_oe2),.O(i_buf_out[0]));
 I_BUF ibuf_inst2 (.I(in[1]),.EN(ibuf_oe3),.O(i_buf_out[1]));
 I_BUF ibuf_inst4 (.I(rst),.EN(ibuf_oe4),.O(rst_i_buf_out));
 
-DFFRE ff_inst1 (.D(oddr_out),.R(rst_i_buf_out),.E(1'b1),.C(clk_buf_out),.Q(dffre_out));
+DFFRE ff_inst1 (.D(i_buf_out[0]),.R(rst_i_buf_out),.E(1'b1),.C(clk_buf_out),.Q(oddr_in));
+DFFRE ff_inst2 (.D(i_buf_out[1]),.R(rst_i_buf_out),.E(1'b1),.C(clk_buf_out),.Q(o_buf_ds_in));
 
 endmodule