Merge pull request #402 from os-fpga/design200

udpated simulator to iverilog for design200

Author: NadeemYaseen

RTL_testcases/verilog_random_designs/design200_30_25_top/raptor_run.sh

@@ -7,7 +7,7 @@ start=`date +%s`
 design="design200_30_25_top"
 ip_name="" #design_level
 #select tool (verilator, vcs, ghdl, iverilog)
-tool_name="verilator" 
+tool_name="iverilog" 
 
 #simulation stages
 post_synth_sim=true