Merge pull request #428 from os-fpga/EDA-3187-add-setup-lec-sim

Eda 3187 add setup lec sim

Author: NadeemYaseen

RTL_testcases/RS_FPGA_PRIMITIVES_new/carry_chain_primitive_inst/raptor_run.sh

@@ -10,7 +10,7 @@ ip_name="" #design_level
 tool_name="iverilog" 
 
 #simulation stages
-post_synth_sim=false 
+post_synth_sim=true 
 post_route_sim=true 
 bitstream_sim=false
 
@@ -259,6 +259,10 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "clear_simulation_files">>raptor_tcl.tcl 
+    echo "setup_lec_sim 10 2">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

RTL_testcases/RTL_Benchmarks_Gap_Analysis/ca_prng/raptor_run.sh

@@ -258,6 +258,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim">>raptor_tcl.tcl  
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

RTL_testcases/RTL_Benchmarks_Gap_Analysis/can/raptor_run.sh

@@ -10,8 +10,8 @@ ip_name="" #design_level
 tool_name="iverilog" 
 
 #simulation stages
-post_synth_sim=true 
-post_route_sim=true 
+post_synth_sim=false 
+post_route_sim=false 
 bitstream_sim=false
 
 #raptor options
@@ -203,20 +203,35 @@ parse_cga exit 1; }
 
     ##vary design to design
     [ -z "$add_constraint_file" ] && echo "" || echo "add_constraint_file $add_constraint_file">>raptor_tcl.tcl 
+    
+    if [ "$post_synth_sim" == true ] || [ "$post_route_sim" == true ] || [ "$bitstream_sim" == true ]; then
+        echo "add_simulation_file ./sim/co_sim_tb/co_sim_$design.v ./rtl/$design.v">>raptor_tcl.tcl 
+        echo "set_top_testbench co_sim_$design">>raptor_tcl.tcl 
+    else
+        echo ""
+    fi
 
 	echo "analyze">>raptor_tcl.tcl
     [ -z "$verific_parser" ] && echo "" || echo "verific_parser $verific_parser">>raptor_tcl.tcl
     [ -z "$synthesis_type" ] && echo "" || echo "synthesis_type $synthesis_type">>raptor_tcl.tcl
     [ -z "$custom_synth_script" ] && echo "" || echo "custom_synth_script $custom_synth_script">>raptor_tcl.tcl
     [ -z "$synth_options" ] && echo "" || echo "synth_options $synth_options">>raptor_tcl.tcl
     [ -z "$strategy" ] && echo "" || echo "synthesize $strategy">>raptor_tcl.tcl  
-    
-    if [ "$post_synth_sim" == true ] || [ "$post_route_sim" == true ] || [ "$bitstream_sim" == true ]; then
-        echo "setup_lec_sim 2 2">>raptor_tcl.tcl
-    else
-        echo ""
-    fi
     if [ "$post_synth_sim" == true ]; then 
+        echo "# Open the input file in read mode">>raptor_tcl.tcl 
+        echo "set input_file [open \"$design/run_1/synth_1_1/synthesis/$design\_post_synth.v\" r]">>raptor_tcl.tcl 
+        echo "# Read the file content">>raptor_tcl.tcl 
+        echo "set file_content [read \$input_file]">>raptor_tcl.tcl 
+        echo "# Close the input file after reading">>raptor_tcl.tcl 
+        echo "close \$input_file">>raptor_tcl.tcl 
+        echo "set modified_content [string map {\"$design(\" \"${design}_post_synth(\"} \$file_content]">>raptor_tcl.tcl 
+        echo "# Open the file again, this time in write mode to overwrite the old content">>raptor_tcl.tcl 
+        echo "set output_file [open \"$design/run_1/synth_1_1/synthesis/$design\_post_synth.v\" w]">>raptor_tcl.tcl
+        echo "# Write the modified content back to the file">>raptor_tcl.tcl 
+        echo "puts \$output_file \$modified_content">>raptor_tcl.tcl 
+        echo "# Close the file">>raptor_tcl.tcl 
+        echo "close \$output_file">>raptor_tcl.tcl 
+        echo "puts \"Modification completed.\"">>raptor_tcl.tcl 
         [ "$tool_name" = "iverilog" ] && echo "simulation_options compilation icarus gate" >> raptor_tcl.tcl || echo "simulation_options compilation verilator gate" >> raptor_tcl.tcl
         [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
     else
@@ -235,11 +250,28 @@ parse_cga exit 1; }
     echo "place">>raptor_tcl.tcl  
     echo "route">>raptor_tcl.tcl  
         if [ "$post_route_sim" == true ]; then 
-            [ "$tool_name" = "iverilog" ] && echo "simulation_options compilation icarus pnr" >> raptor_tcl.tcl || echo "simulation_options compilation verilator pnr" >> raptor_tcl.tcl
+            echo "# Open the input file in read mode">>raptor_tcl.tcl 
+            echo "set input_file [open \"$design/run_1/synth_1_1/synthesis/post_pnr_wrapper_$design\_post_synth.v\" r]">>raptor_tcl.tcl 
+            echo "# Read the file content">>raptor_tcl.tcl 
+            echo "set file_content [read \$input_file]">>raptor_tcl.tcl 
+            echo "# Close the input file after reading">>raptor_tcl.tcl 
+            echo "close \$input_file">>raptor_tcl.tcl 
+            echo "set modified_content [string map {\"module $design(\" \"module ${design}_post_route (\"} \$file_content]">>raptor_tcl.tcl 
+            echo "# Open the file again, this time in write mode to overwrite the old content">>raptor_tcl.tcl 
+            echo "set output_file [open \"$design/run_1/synth_1_1/synthesis/post_pnr_wrapper_$design\_post_synth.v\" w]">>raptor_tcl.tcl
+            echo "# Write the modified content back to the file">>raptor_tcl.tcl 
+            echo "puts \$output_file \$modified_content">>raptor_tcl.tcl 
+            echo "# Close the file">>raptor_tcl.tcl 
+            echo "close \$output_file">>raptor_tcl.tcl 
+            echo "puts \"Modification completed.\"">>raptor_tcl.tcl 
+            [ "$tool_name" = "iverilog" ] && echo "simulation_options compilation icarus -DPNR=1 pnr" >> raptor_tcl.tcl || echo "simulation_options compilation verilator -DPNR=1 pnr" >> raptor_tcl.tcl
             [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
         else
             echo ""
         fi
+    echo "setup_lec_sim">>raptor_tcl.tcl  
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

RTL_testcases/RTL_Benchmarks_Gap_Analysis/cf_fft_256_8/raptor_run.sh

@@ -205,6 +205,8 @@ parse_cga exit 1; }
     [ -z "$custom_synth_script" ] && echo "" || echo "custom_synth_script $custom_synth_script">>raptor_tcl.tcl
     [ -z "$synth_options" ] && echo "" || echo "synth_options $synth_options">>raptor_tcl.tcl
     [ -z "$strategy" ] && echo "" || echo "synthesize $strategy">>raptor_tcl.tcl  
+    echo "setup_lec_sim">>raptor_tcl.tcl  
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
     if [ "$post_synth_sim" == true ]; then 
         echo "# Open the input file in read mode">>raptor_tcl.tcl 
         echo "set input_file [open \"$design/run_1/synth_1_1/synthesis/$design\_post_synth.v\" r]">>raptor_tcl.tcl 
@@ -258,6 +260,7 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

RTL_testcases/RTL_Benchmarks_Gap_Analysis/cf_fft_256_8/rtl/cf_fft_256_8.v

@@ -1123,22 +1123,22 @@ reg    n1960;
 reg    n1964;
 reg    [5:0] n1970;
 reg    n1977;
-reg    n1982;
+reg    n1982 = 0;
 wire   [31:0] n1993;
 reg    [5:0] n1993ra;
-reg    [31:0] n1993m ;
+reg    [31:0] n1993m = 0;
 wire   [31:0] n1997;
 reg    [5:0] n1997ra;
-reg    [31:0] n1997m ;
-reg    n2001;
+reg    [31:0] n1997m = 0;
+reg    n2001 = 0;
 reg    [5:0] n2007;
 reg    n2014;
 wire   [31:0] n2030;
 reg    [5:0] n2030ra;
-reg    [31:0] n2030m ;
+reg    [31:0] n2030m = 0;
 wire   [31:0] n2034;
 reg    [5:0] n2034ra;
-reg    [31:0] n2034m ;
+reg    [31:0] n2034m = 0;
 reg    n2038;
 reg    n2047;
 assign n4 = 7'b0000001;