Autoformat Python and C code

Author: Xeratec

.clang-format

@@ -0,0 +1,7 @@
+IndentWidth: 4
+ColumnLimit: 120
+AlignEscapedNewlines: DontAlign
+SortIncludes: false
+AllowShortFunctionsOnASingleLine: None
+AllowShortIfStatementsOnASingleLine: true
+AllowShortLoopsOnASingleLine: true

.github/workflows/format.yml

@@ -0,0 +1,35 @@
+# Copyright (c) 2022 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# Author:  Jannis Schönleber <janniss@iis.ee.ethz.ch>
+
+name: lint-format
+
+on:
+  workflow_dispatch:
+  push:
+    branches:
+      - '**'
+
+jobs:
+  lint-python:
+    runs-on: ubuntu-latest
+    steps:
+    - name: Check Python with black
+      uses: rickstaa/action-black@v1
+      with:
+        black_args: ". --check"
+
+  lint-cxx:
+    runs-on: ubuntu-latest
+    steps:
+    -
+      name: Checkout
+      uses: actions/checkout@v4
+    -
+      name: Run Clang-format
+      uses: DoozyX/clang-format-lint-action@v0.18.2
+      with:
+        extensions: 'c,h,cpp'
+        clangFormatVersion: 17

.github/workflows/license.yml

@@ -22,4 +22,7 @@ jobs:
           SPDX-License-Identifier: (SHL-0.51|Apache-2.0)
         exclude_paths: |
           deps
-          include/version.h
+          include/version.h
+          ihp13
+          klayout/def2gds.sh
+          klayout/def2stream.py

Bender.yml

@@ -1,4 +1,4 @@
-# Copyright 2024 ETH Zurich and University of Bologna
+# Copyright (c) 2024 ETH Zurich and University of Bologna
 # Solderpad Hardware License, Version 0.51, see LICENSE for details.
 # SPDX-License-Identifier: SHL-0.51
 
@@ -18,7 +18,7 @@ dependencies:
   timer_unit:           { git: "https://github.com/pulp-platform/timer_unit.git",           version: 1.0.3  }
   obi:                  { git: "https://github.com/pulp-platform/obi.git",                  version: 0.1.3  }
   apb_uart:             { git: "https://github.com/pulp-platform/apb_uart.git",             version: 0.2.1  }
-  cve2:                 { path: "rtl/cve2" } # a vendor package (no Bender.yml), see below 
+  cve2:                 { path: "rtl/cve2" } # a vendor package (no Bender.yml), see below
 
 
 sources:
@@ -53,7 +53,7 @@ sources:
     files:
       # Level 0
       - rtl/croc_chip.sv
-  
+
   # netlist for simulation
   - target: netlist_yosys
     files:

Makefile

@@ -34,7 +34,7 @@ checkout: $(IHP_RCX_FILE)
 	$(BENDER) checkout
 	git submodule update --init --recursive
 
-$(IHP_RCX_FILE): 
+$(IHP_RCX_FILE):
 	curl -L -o $@ $(IHP_RCX_URL)
 
 ## Reset dependencies (without updating Bender.lock)
@@ -151,13 +151,26 @@ help: Makefile
 
 .PHONY: help
 
+###########
+# Format  #
+###########
+CLANG_FORMAT_EXECUTABLE ?= clang-format
+
+## Automatically format the code using clang-format and black
+format:
+	@echo -e "\033[1m-> Formatting Python Code...\033[0m"
+	@black */*.py
+	@echo -e "\033[1m-> Formatting C Code...\033[0m"
+	@python scripts/run_clang_format.py -ir sw/ --clang-format-executable=$(CLANG_FORMAT_EXECUTABLE)
+
+.PHONY: format
 
 ###########
 # Cleanup #
 ###########
 
 ## Delete generated files and directories
-clean: 
+clean:
 	rm -f $(SV_FLIST)
 	rm -f klayout/croc_chip.gds
 	rm -rf verilator/obj_dir/

klayout/def2stream.py

@@ -12,7 +12,7 @@
 tech.load(tech_file)
 layoutOptions = tech.load_layout_options
 if len(layer_map) > 0:
-  layoutOptions.lefdef_config.map_file = layer_map
+    layoutOptions.lefdef_config.map_file = layer_map
 
 # Load def file
 main_layout = pya.Layout()
@@ -21,7 +21,7 @@
 
 print("[INFO] Reporting cells after loading DEF ...")
 for i in main_layout.each_cell():
- print("[INFO] '{0}'".format(i.name))
+    print("[INFO] '{0}'".format(i.name))
 
 # Clear cells
 top_cell_index = main_layout.cell(design_name).cell_index()
@@ -30,17 +30,17 @@
 #  - KLayout is prepending VIA_ when reading DEF that instantiates LEF's via
 print("[INFO] Clearing cells...")
 for i in main_layout.each_cell():
-  if i.cell_index() != top_cell_index:
-    if not i.name.startswith("VIA_"):
-      i.clear()
+    if i.cell_index() != top_cell_index:
+        if not i.name.startswith("VIA_"):
+            i.clear()
 
 # Load in the gds to merge
 print("[INFO] Merging GDS/OAS files...")
-with open(gds_flist, 'rb') as file:
+with open(gds_flist, "rb") as file:
     in_files_list = file.read()
 for fil in in_files_list.split():
-  print("\t{0}".format(fil))
-  main_layout.read(fil)
+    print("\t{0}".format(fil))
+    main_layout.read(fil)
 
 # Copy the top level only to a new layout
 print("[INFO] Copying toplevel cell '{0}'".format(design_name))
@@ -52,32 +52,38 @@
 print("[INFO] Checking for missing cell from GDS/OAS...")
 missing_cell = False
 regex = None
-if 'GDS_ALLOW_EMPTY' in os.environ:
+if "GDS_ALLOW_EMPTY" in os.environ:
     print("[INFO] Found GDS_ALLOW_EMPTY variable.")
-    regex = os.getenv('GDS_ALLOW_EMPTY')
+    regex = os.getenv("GDS_ALLOW_EMPTY")
 for i in top_only_layout.each_cell():
-  if i.is_empty():
-    missing_cell = True
-    if regex is not None and re.match(regex, i.name):
-        print("[WARNING] LEF Cell '{0}' ignored. Matches GDS_ALLOW_EMPTY.".format(i.name))
-    else:
-        print("[ERROR] LEF Cell '{0}' has no matching GDS/OAS cell."
-              " Cell will be empty.".format(i.name))
-        errors += 1
+    if i.is_empty():
+        missing_cell = True
+        if regex is not None and re.match(regex, i.name):
+            print(
+                "[WARNING] LEF Cell '{0}' ignored. Matches GDS_ALLOW_EMPTY.".format(
+                    i.name
+                )
+            )
+        else:
+            print(
+                "[ERROR] LEF Cell '{0}' has no matching GDS/OAS cell."
+                " Cell will be empty.".format(i.name)
+            )
+            errors += 1
 
 if not missing_cell:
-  print("[INFO] All LEF cells have matching GDS/OAS cells")
+    print("[INFO] All LEF cells have matching GDS/OAS cells")
 
 print("[INFO] Checking for orphan cell in the final layout...")
 orphan_cell = False
 for i in top_only_layout.each_cell():
-  if i.name != design_name and i.parent_cells() == 0:
-    orphan_cell = True
-    print("[ERROR] Found orphan cell '{0}'".format(i.name))
-    errors += 1
+    if i.name != design_name and i.parent_cells() == 0:
+        orphan_cell = True
+        print("[ERROR] Found orphan cell '{0}'".format(i.name))
+        errors += 1
 
 if not orphan_cell:
-  print("[INFO] No orphan cells")
+    print("[INFO] No orphan cells")
 
 
 # Write out the GDS

project.toml

@@ -0,0 +1,11 @@
+# Copyright 2025 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Philip Wiese <wiesep@iis.ee.ethz.ch>
+
+[tool.black]
+line-length = 120
+target-version = ['py38']
+include = '\\.pyi?$'
+exclude = ''

rtl/soc_ctrl/soc_ctrl.h

@@ -4,7 +4,7 @@
 // Copyright 2024 ETH Zurich and University of Bologna
 
 // Licensing information found in source file:
-// 
+//
 // SPDX-License-Identifier: SHL-0.51
 
 #ifndef _SOC_CTRL_REG_DEFS_
@@ -31,10 +31,10 @@ extern "C" {
 #define SOC_CTRL_BOOTMODE_BOOTMODE_MASK 0x3
 #define SOC_CTRL_BOOTMODE_BOOTMODE_OFFSET 0
 #define SOC_CTRL_BOOTMODE_BOOTMODE_FIELD \
-  ((bitfield_field32_t) { .mask = SOC_CTRL_BOOTMODE_BOOTMODE_MASK, .index = SOC_CTRL_BOOTMODE_BOOTMODE_OFFSET })
+    ((bitfield_field32_t){.mask = SOC_CTRL_BOOTMODE_BOOTMODE_MASK, .index = SOC_CTRL_BOOTMODE_BOOTMODE_OFFSET})
 
 #ifdef __cplusplus
-}  // extern "C"
+} // extern "C"
 #endif
-#endif  // _SOC_CTRL_REG_DEFS_
-// End generated register defines for safety_soc_ctrl
+#endif // _SOC_CTRL_REG_DEFS_
+       // End generated register defines for safety_soc_ctrl