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[AMD] Remove the deprecated C10_WARP_SIZE #9356

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Merged
merged 2 commits into from
Aug 22, 2025
+5 −3
Merged

[AMD] Remove the deprecated C10_WARP_SIZE #9356

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6756d0e
Remove the deprecated C10_WARP_SIZE
hubertlu-tw Aug 19, 2025
d57baa6
Merge branch 'main' into sgl_kernel
HaiShaw Aug 20, 2025
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8 changes: 5 additions & 3 deletions sgl-kernel/include/utils.h
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Original file line number Diff line number Diff line change
Expand Up @@ -331,9 +331,11 @@ inline bool getEnvEnablePDL() {
#ifndef USE_ROCM
#define WARP_SIZE 32
#else
#include <ATen/cuda/CUDAContext.h>
#include <c10/macros/Macros.h>
#define WARP_SIZE C10_WARP_SIZE
#if defined(__GFX9__) || !defined(__HIP_DEVICE_COMPILE__)
#define WARP_SIZE 64
#else
#define WARP_SIZE 32
#endif
Comment on lines +334 to +338
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critical

This change correctly removes the deprecated C10_WARP_SIZE. However, by defining WARP_SIZE as 64 for GFX9+ architectures, it introduces a bug in the warpReduceMax function (lines 400-407), which is hardcoded for a warp size of 32.

With WARP_SIZE=64, warpReduceMax will only perform a partial reduction, leading to incorrect results. The blockReduceMax function (line 409) will also be affected as it relies on both warpReduceMax and WARP_SIZE.

To fix this, warpReduceMax must be updated to handle a 64-wide warp. Here is a suggested implementation:

__device__ __forceinline__ float warpReduceMax(float value) {
#if WARP_SIZE == 64
  value = fmaxf(value, __shfl_xor_sync(FULL_MASK, value, 32));
#endif
  value = fmaxf(value, __shfl_xor_sync(FULL_MASK, value, 16));
  value = fmaxf(value, __shfl_xor_sync(FULL_MASK, value, 8));
  value = fmaxf(value, __shfl_xor_sync(FULL_MASK, value, 4));
  value = fmaxf(value, __shfl_xor_sync(FULL_MASK, value, 2));
  value = fmaxf(value, __shfl_xor_sync(FULL_MASK, value, 1));
  return value;
}

#endif

#ifdef USE_ROCM
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