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Add Qwen3-30B-A3B-Thinking-2507 support on AMD GPUs. #9456

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Add Qwen3-30B-A3B-Thinking-2507 support on AMD GPUs. #9456

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458338a
Add Qwen3-30B-A3B-Thinking-2507 support.
sogalin Aug 21, 2025
965ac51
Fix import issue for silu and gelu.
sogalin Aug 21, 2025
8e74fa6
Merge branch 'main' into Qwen
sogalin Aug 21, 2025
89f06c0
Merge branch 'sgl-project:main' into Qwen
sogalin Aug 21, 2025
cb35bb2
Fix gelu case.
sogalin Aug 21, 2025
eb6f76e
Use aiter's get_rope and fix qwen2 get_rope
hubertlu-tw Aug 21, 2025
1ff271d
Generalize aiter's get_rope usage
hubertlu-tw Aug 21, 2025
7c1726d
Fix get_rope
hubertlu-tw Aug 21, 2025
724f566
Merge branch 'main' into Qwen
hubertlu-tw Aug 22, 2025
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25 changes: 18 additions & 7 deletions python/sglang/srt/layers/moe/fused_moe_triton/fused_moe.py
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Original file line number Diff line number Diff line change
Expand Up @@ -49,13 +49,15 @@
elif _is_cpu and _is_cpu_amx_available:
pass
elif _is_hip:
from vllm import _custom_ops as vllm_ops # gelu_and_mul, silu_and_mul
from sgl_kernel import gelu_and_mul, silu_and_mul

if _use_aiter:
try:
from aiter import moe_sum
except ImportError:
raise ImportError("aiter is required when SGLANG_USE_AITER is set to True")
else:
from vllm import _custom_ops as vllm_ops


if _is_cuda or _is_hip:
Expand Down Expand Up @@ -1537,7 +1539,7 @@ def fused_experts_impl(
gemm1_alpha,
gemm1_limit,
)
elif _is_cuda:
elif _is_cuda or _is_hip:
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There is another gelu_and_mul can be imported from sgl_kernel when _is_hip ==True.

silu_and_mul(intermediate_cache1.view(-1, N), intermediate_cache2)
else:
vllm_ops.silu_and_mul(
Expand All @@ -1546,7 +1548,7 @@ def fused_experts_impl(
elif activation == "gelu":
assert gemm1_alpha is None, "gemm1_alpha is not supported for gelu"
assert gemm1_limit is None, "gemm1_limit is not supported for gelu"
if _is_cuda:
if _is_cuda or _is_hip:
gelu_and_mul(intermediate_cache1.view(-1, N), intermediate_cache2)
else:
vllm_ops.gelu_and_mul(
Expand Down Expand Up @@ -1619,10 +1621,19 @@ def fused_experts_impl(
out_hidden_states[begin_chunk_idx:end_chunk_idx],
)
else:
vllm_ops.moe_sum(
intermediate_cache3.view(*intermediate_cache3.shape),
out_hidden_states[begin_chunk_idx:end_chunk_idx],
)
# According to micro benchmark results, torch.compile can get better performance for small token.
if tokens_in_chunk <= 32:
moe_sum_reduce_torch_compile(
intermediate_cache3.view(*intermediate_cache3.shape),
out_hidden_states[begin_chunk_idx:end_chunk_idx],
routed_scaling_factor,
)
else:
moe_sum_reduce_triton(
intermediate_cache3.view(*intermediate_cache3.shape),
out_hidden_states[begin_chunk_idx:end_chunk_idx],
routed_scaling_factor,
)
Comment on lines +1624 to +1636
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medium

This block of code for HIP is nearly identical to the logic for CUDA in lines 1602-1614. This code duplication can be avoided by refactoring and combining the logic for both _is_cuda and _is_hip, for example by using elif _is_cuda or _is_hip:. This would improve maintainability. Additionally, the CUDA path includes optimizations for topk values of 1 and 2, which could also be beneficial for the HIP path.

else:
vllm_ops.moe_sum(
intermediate_cache3.view(*intermediate_cache3.shape),
Expand Down
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