#Router 1X3 Physical Design
-
Notifications
You must be signed in to change notification settings - Fork 0
Executed the complete physical design flow of a 1x3 router, encompassing synthesis, floorplanning, placement, clock tree synthesis, routing, and static timing analysis using Synopsys Fusion Compiler on a 32nm technology node.
shrishail7/Router_1X3_PD
Folders and files
| Name | Name | Last commit message | Last commit date | |
|---|---|---|---|---|
Repository files navigation
About
Executed the complete physical design flow of a 1x3 router, encompassing synthesis, floorplanning, placement, clock tree synthesis, routing, and static timing analysis using Synopsys Fusion Compiler on a 32nm technology node.