Layout of 4bit Ripple Carry Adder formed using CMOS logic in gpdk180nm technology node done in Cadence Virtuoso with no DRC and LVS errors.
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Aug 7, 2024
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cmos-logic
Here are 8 public repositories matching this topic...
This repository contains the design, simulation, and performance evaluation of a CMOS NAND Gate using Cadence Virtuoso. The project highlights the design principles and operational characteristics of a fundamental digital logic gate implemented with CMOS technology.
layout cadence-virtuoso cadence nmos vlsi-circuits vlsi-design pmos cmos-circuits cmos-vlsi cmos-logic low-power-vlsi-design
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Jan 6, 2025
Performance Analysis of a 4-bit Ripple Carry Adder (RCA) formed using Static CMOS, Transmission Gate, NMOS Pass Transistor Logic at gpdk 180nm Technology node.
projects schematic vlsi cadence-virtuoso propagation-delay power-analysis 4bits ripple-carry-adder cmos-logic pass-transistor-logic transmission-gate-logic
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Apr 26, 2025
High-speed 8×8 Dadda multiplier designed in 45nm CMOS technology with hybrid transmission gate/CMOS logic. Features 4:2 compressor-based partial product reduction, critical path delay of 0.204ns, and comprehensive delay & power analysis.
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Mar 10, 2025
180nm CMOS Design And Implementation of a Seven Segment Display Controller Using a 4-bit Binary Input (The repository with same name is created long ago and a new repository with the same name is created later and the contents in the repository is updated)
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Dec 14, 2024
Designed and simulated all fundamental and universal CMOS logic gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) using the Electric VLSI Design Tool. This project includes schematic design, DRC-clean layouts, ALS simulation, and waveform analysis.
simulation vlsi vlsi-physical-design cmos digital-design vlsi-circuits vlsi-design cmos-inverter cmos-circuits layout-design cmos-logic schematic-design drc-check electric-vlsi-free-tool
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May 10, 2025
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