CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] <Semester IV>

This is the mirror for gitee in github for project assignment of cs202 / 214 Computer Organization course of Southern University of Science and Technology， which is to manufacture a CPU. 这是南方科技大学CS202/214计算机组成原理课程的大作业——实现一个CPU。

21Summer-VE370-Intro-to-Computer-Organization-Projects: -Project1: RISC-V Assembly, simluating c code. -Project2: 1.RISC-V64 single cycle processor. 2.RISC-V64 five-stage pipelined processor. -Project3: Virtual memory, TLB, cache, memory simulator. -Project4: Literature review on Computer Organization.

A 16-Bit computer(C.I.S.C) with 38 Instructions, 2 addressing modes and a register stack.

A simple 32-bit Arithmetic Logic Unit (ALU) capable of performing arithmetic, logical, shift, and comparision operations

Labs of USTC 2020 Spring Computer Organization and Design course

A GUI simulator/interpreter for custom assembly language, written in python/tkinter

An Assembler for Morris Mano's Basic Computer

This rep contains neighbour's cpu. Single-cycle/Multi-cycle CPU implementation in vhdl using ISE Xiling for the course 'Computer Organization' at TUC

Designed using Xilinx Vivado Design Package, a Verilog-based 5-stage 32-bit pipelined and forwarded CPU, which handles Load word, Add, and Jump MIPS format instructions with Forwarding and Writeback units to handle data hazards, reduce possible stalls, and improve performance by 10%.

Single-Cycle 8-bit CPU designed for basic instruction execution with Logisim.

Learning to code in Assembly Language(8086).

Notes for Computer Systems: A Programmer’s Perspective 3rd Edition, Computer organization and design RISC-V 2nd Edition and OSTEP. Also see CSAPP-3e-Solutions.

Computer Organization and Design Solutions.

An educational simulator of Tomasulo’s Algorithm in Rust, with cycle-by-cycle execution and visualizable state.

A cache simulator with LRU policy. Designed to help students build a better understanding of cache mechanisms.