%%file ring4bd.v
module ring4bd(mode, clock, reset, count);
input mode, clock, reset;
output [3:0] count;
reg [3:0] count;
always @(posedge clock or posedge reset)
begin
if(reset)
count = 4'b0001;
else
count = (mode) ? {count[2:0], count[3]} : {count[0], count[3:1]};
end
endmoduleWriting ring4bd.v
%%file ring4bd_test.v
module ring4bd_test;
reg mode, clock, reset;
wire [3:0] count;
initial
begin
clock = 1'b0;
forever
#50 clock = ~clock;
end
initial
begin
reset = 1'b1;
mode = 1;
#200 reset = 1'b0;
#100 mode=1;
#800 mode=0;
#1600 $finish;
end
initial
begin
$monitor($time, "mode = %b, \tclock = %d, \treset = %d, \tcount = %b", mode, clock, reset, count);
end
ring4bd dut(mode, clock, reset, count);
initial
begin
$display("Inside hierarchy: %m ");
$dumpfile("ring4bd2.vcd");
$dumpvars(0, ring4bd_test);
end
endmoduleWriting ring4bd_test.v
from PyMTI import *
import subprocess
vcd_name = "ring4bd2.vcd"
save_name = "ring4bd2.svg"
do_name = "helloworld.do"
do_name2 = "helloworld2.do"
save_title = "Sample Timing Model"
verilog_files = ["ring4bd.v", "ring4bd_test.v"]
if __name__ == "__main__":
modules = parse_verilog_files(verilog_files)
modules = find_module_instances(verilog_files, modules)
print_summary(modules)
top_modules = find_top_modules(modules)
if not top_modules:
print("[ERROR] No top module detected!")
exit(1)
print(f"Top module(s) detected: {top_modules}")
top_module = top_modules[0]
generate_do_file(modules, verilog_files, top_module, do_filename=do_name, sim_time=3600)
subprocess.run(["vsim", "-c", "-do", do_name])
signals = (
("ring4bd_test.mode", "mode"),
("ring4bd_test.clock", "Clock"),
("ring4bd_test.reset", "Reset"),
("ring4bd_test.count[3]", "count[3]"),
("ring4bd_test.count[2]", "count[2]"),
("ring4bd_test.count[1]", "count[1]"),
("ring4bd_test.count[0]", "count[0]"),
)
analog_signal = ("ring4bd_test.dut.clock","Analog Signal")
plot(vcd_name, save_name, save_title, signals, analog_signal)=== Design Summary ===
Module: ring4bd
Ports:
input mode :
input clock :
input reset :
output count : [3:0]
Instantiates: ring4bd
Module: ring4bd_test
Ports:
Instantiates: ring4bd
Top module(s) detected: ['ring4bd_test']
[INFO] Generated ModelSim DO file 'helloworld.do' for top module 'ring4bd_test'
from PyMTI import *
import subprocess
vcd_name = "ring4bd2.vcd"
save_name = "ring4bd2.svg"
do_name = "helloworld.do"
do_name2 = "helloworld2.do"
save_title = "Sample Timing Model"
verilog_files = ["ring4bd.v", "ring4bd_test.v"]
do_file_content = """
##################################
# A very simple modelsim do file #
##################################
# 1) Create a library for working in
vlib work
# 2) Compile the half adder
#vcom -93 -explicit -work work HalfAdder.vhd
# 2) Compile the half adder
vlog ring4bd.v
vlog ring4bd_test.v
# 3) Load it for simulation
vsim ring4bd_test
# 4) Open some selected windows for viewing
view structure
view signals
view wave
# 5) Show some of the signals in the wave window
add wave -noupdate -divider -height 32 Inputs
add wave -noupdate mode
add wave -noupdate clock
add wave -noupdate reset
add wave -noupdate -divider -height 32 Outputs
add wave -noupdate count
# 6) Set some test patterns
# a = 0, b = 0 at 0 ns
#force a 0 0
#force b 0 0
# a = 1, b = 0 at 10 ns
#force a 1 10
# a = 0, b = 1 at 20 ns
#force a 0 20
#force b 1 20
# a = 1, b = 1 at 30 ns
#force a 1 30
# 7) Run the simulation for 3600 ns
run 3600
quit -f
"""
with open(do_name2, "w") as file:
file.write(do_file_content)
if __name__ == "__main__":
modules = parse_verilog_files(verilog_files)
modules = find_module_instances(verilog_files, modules)
print_summary(modules)
top_modules = find_top_modules(modules)
if not top_modules:
print("[ERROR] No top module detected!")
exit(1)
print(f"Top module(s) detected: {top_modules}")
top_module = top_modules[0]
generate_do_file(modules, verilog_files, top_module, do_filename=do_name2, sim_time=3600)
subprocess.run(["vsim", "-c", "-do", do_name2])
signals = (
("ring4bd_test.mode", "mode"),
("ring4bd_test.clock", "Clock"),
("ring4bd_test.reset", "Reset"),
("ring4bd_test.count[3]", "count[3]"),
("ring4bd_test.count[2]", "count[2]"),
("ring4bd_test.count[1]", "count[1]"),
("ring4bd_test.count[0]", "count[0]"),
)
analog_signal = ("ring4bd_test.dut.clock","Analog Signal")
plot(vcd_name, save_name, save_title, signals, analog_signal)=== Design Summary ===
Module: ring4bd
Ports:
input mode :
input clock :
input reset :
output count : [3:0]
Instantiates: ring4bd
Module: ring4bd_test
Ports:
Instantiates: ring4bd
Top module(s) detected: ['ring4bd_test']
[INFO] Generated ModelSim DO file 'helloworld2.do' for top module 'ring4bd_test'
Licensing terms for Project PyMTI
This project is licensed under the terms of the 3-Clause BSD License (also known as New or Revised or Modified BSD License, or the BSD-3-Clause license), as follows:
Copyright (c) 2025 M. B. Ghaznavi-Ghoushchi. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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