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Translation entry eviction needs to be handled correctly

bug

Status: Open.

#22 In ymarathe/TLB-Coherence-Simulator;

· ymarathe opened on Mar 15, 2018

Cache to cache transfer needs to be modeled

bug

Status: Open.

#14 In ymarathe/TLB-Coherence-Simulator;

· ymarathe opened on Feb 7, 2018

Coherence logic marks L2 line as modified on a *_WRITE

bug

question

Status: Open.

#13 In ymarathe/TLB-Coherence-Simulator;

· ymarathe opened on Feb 7, 2018

Coherence logic broadcasts *_READ updates incorrectly

bug

Status: Open.

#12 In ymarathe/TLB-Coherence-Simulator;

· ymarathe opened on Feb 7, 2018

Build trace consumption logic into the simulator

bug

Status: Open.

#11 In ymarathe/TLB-Coherence-Simulator;

· ymarathe opened on Feb 7, 2018

Decide on number of outstanding misses at each level

enhancement

question

Status: Open.

#7 In ymarathe/TLB-Coherence-Simulator;

· ymarathe opened on Feb 6, 2018

Add instrumentation counters in each unit

bug

Status: Open.

#5 In ymarathe/TLB-Coherence-Simulator;

· ymarathe opened on Feb 6, 2018

RequestStatus is not propagated upstream in the cache hierarchy

bug

Status: Open.

#2 In ymarathe/TLB-Coherence-Simulator;

· ymarathe opened on Feb 6, 2018

Simulation progresses only if all cores->tick() is called

bug

Status: Open.

#1 In ymarathe/TLB-Coherence-Simulator;

· ymarathe opened on Feb 6, 2018