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error-detection-correction

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StackedArchitect / Fault-Tolerant-RISCV

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A fault-tolerant, pipelined RISC-V processor system implemented in Verilog, featuring Triple Modular Redundancy (TMR), SECDED memory protection, error injection, and robust recovery mechanisms. Designed for research, education, and prototyping of reliable digital systems.

fpga fault-tolerance riscv verilog computer-architecture error-detection-correction triple-modular-redundancy secded pipelined-processor
  • Updated Jun 26, 2025
  • Verilog

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