Add apsk_demo example...

examples/ulxs3/apsk_demo/.gitignore

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+output/
+lextab.py
+yacctab.py

examples/ulxs3/apsk_demo/Makefile

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+# Makefile based on https://github.com/ulx3s/blink/blob/main/Makefile
+.ONESHELL: # Applies to every targets in the file!
+
+PYFILES = lextab.py yacctab.py
+DIR = output/pipelinec_top
+
+all: build prog
+
+build:
+	../../../src/pipelinec apsk_demo.c --top pipelinec_top --out_dir output
+	cp pll.v $(DIR)
+	cp top.v $(DIR)
+
+apsk_demo.json:
+	cd $(DIR)
+	echo  -n "yosys -m ghdl  -p 'ghdl --std=08 -frelaxed " > build.sh
+	cat ../vhdl_files.txt >> build.sh
+	echo "-e pipelinec_top; read_verilog top.v; synth_ecp5 -abc9 -nowidelut -json apsk_demo.json' > ../yosyslog.log " >> build.sh
+	bash build.sh
+
+ulx3s.bit: ulx3s_out.config
+	cd $(DIR)
+	ecppack ulx3s_out.config ulx3s.bit
+
+ulx3s_out.config: apsk_demo.json
+	cd $(DIR)
+	nextpnr-ecp5 --85k --json apsk_demo.json \
+		--pre-pack ../clocks.py --seed 1 \
+		--lpf ../../ulx3s_v20.lpf \
+		--textcfg ulx3s_out.config \
+		--package CABGA381
+
+prog: ulx3s.bit
+	cd $(DIR)
+	fujprog ulx3s.bit
+
+clean:
+	rm -rf output rm ulx3s_out.config ulx3s.bit $(PYFILES)

examples/ulxs3/apsk_demo/README.md

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+# APSK Modulator on FPGA
+
+> [!WARNING]
+>
+> This code was tested on an earlier version of PipelineC within a configured environment, in case of issues feel free to ask for help.
+
+This is a 16-APSK (and, 32-APSK, as a bonus) digital modulator implemented using the [PipelineC](https://github.com/JulianKemmerer/PipelineC) high-level synthesis HDL, running on a Lattice ECP5 (ULX3S) FPGA.
+
+The modulator generates a baseband or RF-shifted signal using a chain of modular components:
+- Pseudo-random data generation (LFSR)
+- APSK symbol mapping
+- CIC interpolation
+- Digital upconversion (DUC)
+- Delta-Sigma DACs (Low-pass & Band-pass)
+
+📖🔗 **[Read the full article on LinkedIn →](https://www.linkedin.com/pulse/16-apsk-modulator-fpga-using-pipelinec-hdl-paulo-dutra-79uce)**
+
+---
+
+## 🔧 Block Diagram
+
+![PipelineC 16-APSK Modulator Block Diagram and Some explanation about the design](images/image.png)
+*PipelineC 16-APSK Modulator Block Diagram and Some explanation about the design*
+
+---
+
+## ⚙️ FPGA Output
+
+### Constellation Output (Baseband)
+
+![Actual Constellation diagram and Spectrum generated by the FPGA Design visualized on a Rigol DHO804 Oscilloscope](images/image-1.png)
+*Actual Constellation diagram and Spectrum generated by the FPGA Design using an external RC low-pass filter, visualized on a Rigol DHO804 Oscilloscope*
+
+---
+
+### RF Output Spectrum (~7.68 MHz)
+
+![Band-Pass Delta Sigma Modulator output spectrum visualized using the FFT of the Rigol DHO804 Oscilloscope](images/image-2.png)
+*Band-Pass Delta Sigma Modulator output spectrum visualized using the FFT of the Rigol DHO804 Oscilloscope.*
+---
+
+## 🔬 Tools & Tech
+
+- **HDL**: [PipelineC](https://github.com/JulianKemmerer/PipelineC) (C-based HLS HDL) + [OSS CAD Suite](https://github.com/YosysHQ/oss-cad-suite-build)
+- **Simulation**: [CocoTB](https://www.cocotb.org/) + [GHDL](https://ghdl.github.io/ghdl/)
+- **Board**: [ULX3S](https://ulx3s.github.io) (Lattice ECP5-85F)
+- **Testbench**: Python, Matplotlib, GTKWave
+- **Output**: Delta-Sigma DACs (2nd Order LP & Band-Pass)
+
+---
+
+## 📎 License
+
+MIT © Paulo Dutra – PU4THZ
+
+---
+
+## 📌 TODO
+- [ ] Test if this still works (many changes on the repo...)
+- [ ] Improve documentation (diagrams, usage, examples)
+
+📫 Feedback and collaboration are welcome!