WIP: Serwb improvements

[cklarhorst]

I decided to make this PR bigger:

My open todos:

• Wait for PR serwb: Fix shifting #14
• s7serdes: Add Virtex7 support
• s7serdes: Allow different serdes data_width options (4,6,8 bits wide)
• s7serdes: Allow serdes width expansion (10,14 bits)
• s7serdes: Allow support for single ended IO
• Add s6serdes implementation(2,4 bits wide)

Current additional ideas:

• s6serdes: Improve the idelay2 range: Use 255 taps for edge detection and just make sure that the delay used is less than the errdata value.. Just use 255 taps. I have not experienced any problems, and it makes the implementation easier (doesn't need to know the sysfreq)

What was tested (sync + memtest over serwb, all with PR#14):

• s7serdes: Virtex7-Virtex7 on custom board (8bit mode, lvds, with s7serdes clocking module, 100mhz sysclk)
• s7serdes: Kintex7-Virtex7 on custom board (4/8bit mode, lvds, shared main clk, 100mhz sysclk)
• s7serdes: Kintex7-Virtex7 on custom board (10bit mode, lvds, shared main clk)
• s7serdes: Virtex7-Virtex7 on custom board (10bit mode, lvds, with s7serdes clocking module)
• s6serdes: Spartan6-Spartan6 (2/4bit, lvcmos33, with S6SerdesClockingSimple, 50mhz sysclk) -> does only sync with taps override to 255 (final delay was in errdata accepted range)

As always, thank you for this great project.
Let me know if there is anything I can improve or do differently to reduce work on your side.

[cklarhorst]

Does somebody know a good way to get the sysfreq, or is it ok to make it a parameter?

[enjoy-digital]

Hi @cklarhorst,

that's indeed a point I want to improve and avoid having to pass sys_clk_freq parameter to all module that require it. (ie having access to it globally when elaborating a design). I'll try to work on such improvements in the future, but for now for this module, if sys_clk_freq is required, you can add an argument (and make it optional with a default value of None).

[enjoy-digital]

Hi @cklarhorst,

thanks for your work, this is really interesting and the changes look good. #14 is now merged and happy to do a closer review of this PR when you think it will be ready.

[cklarhorst]

Thanks. (I have to change my focus for a month, so I will finish this PR sometime at the end of next month.)

[enjoy-digital]

@cklarhorst Sure, no problem.

[cklarhorst]

Hi,
Sorry for the very long delay. I have updated this PR to reflect the latest liteiclink changes.
Nowadays, the SERWBPHY has a clk4x parameter, but for this PR, the clk depends on the serdes_data_width setting.
I don't know which solution is preferable. Would renaming the current parameter from clk4x to clk_serdes be acceptable?
Overall, the SERWBPHY already has parameters that only apply to specific serdes implementation.
Maybe it would be better to change the SERWBPHY init from
def __init__(self, device, pads, mode="master", init_timeout=2**16, clk="sys", clk4x="sys4x", clk_ratio="1:1", clk_delay_taps=0, rx_delay_taps=0, serdes_data_width=8):
to
def __init__(self, serdes, init_timeout=2**16): as all those parameters are only passed through anyway.